TurboCode LLC v. Ceragon Networks Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: TurboCode LLC (Texas)
  • Defendant: Ceragon Networks, Inc. (New Jersey)
  • Plaintiff’s Counsel: Direction IP Law
• Case Identification: 2:25-cv-00383, E.D. Tex., 04/11/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant maintains its principal place of business in Plano, Texas, and has allegedly committed acts of infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s wireless backhaul products, which comply with 4G/LTE communication standards, infringe a patent related to high-speed turbo code decoder architecture.
• Technical Context: The technology at issue involves turbo codes, a form of forward error correction (FEC) essential for ensuring data integrity and high throughput in modern wireless systems like 4G/LTE and 5G.
• Key Procedural History: The patent-in-suit was the subject of an ex parte reexamination, with a Reexamination Certificate issued on February 10, 2009. This proceeding, which confirmed the patentability of the amended claims, may strengthen the patent's presumption of validity against arguments that were or could have been raised during the reexamination.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,813,742 - High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture, issued November 2, 2004

The Invention Explained

• Problem Addressed: The patent addresses the challenge of implementing turbo code decoders for 3G wireless applications. At the time of the invention, existing Maximum a Posteriori (MAP) decoding algorithms were computationally intensive, requiring many complex multiplications that made them slow, costly, and power-hungry, rendering them impractical for mass-market mobile devices (’742 Patent, col. 2:10-28, col. 2:48-61).
• The Patented Solution: The invention proposes a decoder architecture using two pipelined Soft-In/Soft-Out (SISO) decoders operating in a feedback loop. This parallel, pipelined structure allows one decoder to process a block of data while the other receives feedback from a previous decoding iteration, significantly increasing data throughput. The use of "Log-MAP" decoders, which operate in the logarithmic domain, replaces complex multiplication operations with simpler, faster, and lower-power adder circuits, making the design more suitable for implementation in an ASIC (Application-Specific Integrated Circuit) (’742 Patent, Abstract; col. 2:38-51; Fig. 4).
• Technical Importance: This architecture aimed to make high-performance, iterative turbo decoding feasible for consumer-grade 3G devices by increasing speed while reducing hardware complexity, cost, and power consumption (’742 Patent, col. 2:31-40).

Key Claims at a Glance

• The complaint asserts independent claim 6, as amended by the Ex Parte Reexamination Certificate (Compl. ¶¶ 12-13).
• The essential elements of reexamined independent claim 6 include:
  • A method of iteratively decoding a plurality of sequences of received baseband signals.
  • Providing an input buffer with at least three shift registers for receiving an input signal and generating first, second, and third shifted input signals.
  • Providing first and second soft decision decoders serially coupled in a circular circuit, with specific inputs from the buffer.
  • Providing at least one memory module coupled to each decoder's output, where the second decoder's associated memory output is fed back as an input to the first decoder.
  • Processing systematic and extrinsic information data using a maximum a posteriori (MAP) probability algorithm and/or its logarithm approximation.
  • Generating, weighing, and storing soft decision information.
  • Performing iterative decoding for a predetermined number of times in a circular circuit.
• The complaint does not explicitly reserve the right to assert other claims.

III. The Accused Instrumentality

Product Identification

• The complaint names specific wireless backhaul products, including the FibeAir series (IP-20F, IP-20A, IP-20E, IP-20C, IP-20C-HP, IP-20V, IP-20G) and the PointLink Access solution (Compl. ¶12). It also broadly accuses any of Defendant's cellular communication equipment, such as eNodeBs and base stations, that conform to 4G/LTE standards (Compl. ¶¶ 4, 12).

Functionality and Market Context

• The accused products are described as network infrastructure components, such as "split-mount, multicore edge node[s]" and "all-outdoor wireless backhaul node[s]," designed to provide high-capacity connectivity for mobile networks (Compl. ¶14, pp. 5, 8). The complaint alleges these products are marketed for and comply with 3GPP standards for "LTE, LTE-Advanced, LTE-Advanced pro and 5G" (Compl. ¶14, p. 5). The core of the infringement allegation is that compliance with these standards, which mandate the use of turbo coding for error correction, means the products necessarily perform the patented decoding method (Compl. ¶¶ 15-16). A screenshot from a product datasheet shows performance specifications specifically for an "LTE scenario" (Compl. ¶14, p. 7).

IV. Analysis of Infringement Allegations

The complaint does not provide a traditional claim chart exhibit. Instead, it advances its infringement theory by alleging that compliance with 3GPP technical specifications for 4G/LTE inherently requires practicing the claimed method.

’742 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A primary question is whether compliance with a 3GPP encoding standard (e.g., TS 36.212) is sufficient to prove infringement of a decoding method claim. The defense may argue that the standard does not mandate the specific decoder architecture claimed and that non-infringing implementations are possible. The complaint’s argument relies heavily on the inference that a standards-compliant decoder must mirror the structure of the standard's encoder (Compl. ¶¶ 18, 24).
  • Technical Questions: What evidence demonstrates that the accused products implement the specific "circular circuit" with two decoders and the precise feedback path ("output from the last soft decision decoder is fed back as an input to the first") as claimed? The complaint maps these limitations to the general principles of iterative turbo decoding and system-level HARQ feedback (Compl. ¶27), which raises the question of whether this abstract mapping meets the structural limitations of the claim as understood from the patent's specification and figures (’742 Patent, Fig. 4).

V. Key Claim Terms for Construction

• The Term: "first and second soft decision decoders serially coupled in a circular circuit"

  • Context and Importance: This term defines the core architecture of the claimed method. Its construction will determine whether the claim is limited to a specific hardware implementation or can read on a broader range of iterative decoding systems. The dispute will likely center on whether the accused products, by implementing standards-based turbo decoding, necessarily contain this "circular circuit."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not specify a hardware implementation, referring to "decoders" and a "method." Plaintiff may argue this covers any system that performs the functional steps, including a system where the "circular" nature arises from system-level protocols like HARQ (Compl. ¶27).
    • Evidence for a Narrower Interpretation: The patent’s detailed description and figures consistently depict a specific two-decoder, pipelined hardware architecture (’742 Patent, Fig. 4, Fig. 22). The abstract describes "pipelined Log-MAP decoders," and the summary of invention details two decoders functioning "in a pipelined scheme" (’742 Patent, Abstract; col. 2:40-48). This may support a narrower construction limited to such a specific structure.

• The Term: "an output from the last soft decision decoder is fed back as an input to the first soft decision decoder"

  • Context and Importance: This limitation defines the feedback mechanism critical to the iterative process. Practitioners may focus on this term because the complaint maps it to the general concept of iterative decoding in LTE, not to a specific, documented feedback path within the accused products themselves (Compl. ¶23-24).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim uses functional language ("is fed back as an input"). Plaintiff could argue this does not require a direct physical wire but can be satisfied by any process where the output from one decoding stage is used to inform a subsequent stage, as in HARQ.
    • Evidence for a Narrower Interpretation: The patent’s figures, particularly Figure 4 (system block diagram) and Figure 23 (iterative decoding feedback control), illustrate a direct, internal feedback loop within the decoder subsystem itself. A defendant could argue the claim is limited to this disclosed implementation, not a higher-level system feedback mechanism.

VI. Other Allegations

• Indirect Infringement: The complaint does not plead separate counts for indirect or contributory infringement.
• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement or facts to support pre-suit knowledge of the patent.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of standards-based proof: Can Plaintiff prove infringement of a specific decoding method claim solely by showing that Defendant’s products comply with an LTE standard that mandates a corresponding encoding scheme? The case will likely depend on whether the standard dictates the specific architectural and feedback elements of the asserted claim or allows for alternative, non-infringing decoder implementations.

2. The case will also turn on a key question of claim scope: Will the architectural term "serially coupled in a circular circuit" be construed broadly to cover the functional data flow in any iterative turbo decoding system, as Plaintiff's infringement theory suggests, or will it be limited to the specific two-decoder, pipelined hardware arrangement heavily featured in the patent’s specification?