2:25-cv-00596
Mr Licensing LLC v. Seagate Technology Holdings
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: MR Licensing LLC (Texas)
- Defendant: Seagate Technology Holdings plc (Ireland), et al. (collectively "Seagate")
- Plaintiff’s Counsel: Fabricant LLP; The Davis Firm, PC
- Case Identification: 2:25-cv-00596, E.D. Tex., 06/02/2025
- Venue Allegations: Venue is alleged as proper under 28 U.S.C. § 1391(c) on the basis that the defendants are foreign corporations subject to personal jurisdiction within the district, and thus may be sued in any judicial district.
- Core Dispute: Plaintiff alleges that Defendant’s data storage products, including various solid-state drives and self-encrypting hard drives, infringe eight patents related to memory device architecture, data relocation techniques, and secure data management.
- Technical Context: The technologies at issue concern methods for improving the performance, longevity, and security of non-volatile memory systems, which are foundational components in consumer electronics, data centers, and enterprise storage.
- Key Procedural History: The complaint alleges that the prior assignee of the patents, Monterey Research, notified Seagate of its infringement of several of the patents-in-suit in a series of communications during 2020 and 2021. Seagate allegedly responded that it was not interested in licensing the technology, a fact pattern Plaintiff cites to support its allegations of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2007-12-21 | Earliest Priority Date ('776, '303 Patents) |
| 2007-12-28 | Earliest Priority Date ('041, '611, '049, '383, '847 Patents) |
| 2008-03-25 | Earliest Priority Date ('658 Patent) |
| 2011-07-12 | U.S. Patent No. 7,979,658 Issued |
| 2012-08-07 | U.S. Patent No. 8,239,611 Issued |
| 2014-04-08 | U.S. Patent No. 8,694,776 Issued |
| 2017-08-15 | U.S. Patent No. 9,734,049 Issued |
| 2017-09-19 | U.S. Patent No. 9,767,303 Issued |
| 2019-02-12 | U.S. Patent No. 10,204,041 Issued |
| 2020-07-27 | Monterey Research sends Seagate notice letter re: '303, '658, '776 Patents |
| 2020-10-08 | Monterey Research sends follow-up letter |
| 2020-10-15 | Seagate replies it is not interested in licensing |
| 2020-10-26 | Longitude Licensing Limited sends follow-up letter |
| 2021-01-22 | Monterey Research sends Seagate notice letter re: '611, '049, '041 Patents |
| 2021-08-17 | U.S. Patent No. 11,093,383 Issued |
| 2023-03-21 | U.S. Patent No. 11,609,847 Issued |
| 2025-06-02 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 10,204,041 - "Relocating Data in a Memory Device," issued February 12, 2019
The Invention Explained
- Problem Addressed: The patent’s background section describes the challenge of managing flash memory, which has a finite lifespan due to wear from program and erase cycles. It notes that conventional memory controller components can become performance bottlenecks when tasked with both basic data access operations and resource-intensive background functions like wear leveling and garbage collection. (Compl. ¶12; ’041 Patent, col. 1:24-42, col. 3:5-13).
- The Patented Solution: The invention proposes a memory device architecture with two functionally distinct and independent processing components. A "memory controller module" handles routine "lower level" host requests like reading and writing data, while a separate "memory manager module" handles "higher level," computationally intensive maintenance tasks such as relocating data to less worn blocks (wear leveling). This division of labor allows the device to service host requests more efficiently. (’041 Patent, Abstract; Fig. 1; col. 2:50-59).
- Technical Importance: This dual-processor architecture allows for the parallel processing of host-facing data operations and internal memory maintenance, which can improve overall device performance and extend the usable life of the flash memory. (’041 Patent, col. 3:10-13).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1. (Compl. ¶35).
- The essential elements of Claim 1 are:
- A method for relocating data in a device comprising:
- first performing, using a memory controller module, a lower level memory operation (e.g., read, write) on a first bus;
- determining, using a memory manager module that is independent of the controller module, to relocate data based on a criterion; and
- second performing, using the memory manager module, a higher level memory operation comprising moving data to a less worn memory location on the first bus;
- wherein the first performing is at least partially concurrent with, but independently from, the determining; and
- wherein the first performing utilizes the controller module without utilizing the manager module.
U.S. Patent No. 7,979,658 - "Secure Management of Memory Regions in a Memory," issued July 12, 2011
The Invention Explained
- Problem Addressed: The patent addresses the security risk that data "deleted" from a device may not be truly erased, leaving sensitive information potentially recoverable. It identifies a need for robust, hardware-level controls for managing access to and ensuring the secure removal of data from distinct memory regions. (Compl. ¶13; ’658 Patent, col. 1:30-47).
- The Patented Solution: The invention describes a system with an "access management component" integrated within the memory device itself. This component controls access to different memory regions by comparing received authentication data to stored credentials. Upon successful authentication, it can facilitate a "wipe erase" of a memory region, rendering the data permanently inaccessible, and subsequently create a new security record with a default credential to reset access control for that region. (’658 Patent, Abstract; Fig. 1).
- Technical Importance: By embedding the access control and erase logic directly into the memory component, the invention provides a more secure framework than purely software-based solutions, which can be more easily bypassed or corrupted. (’658 Patent, col. 2:59-68).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1. (Compl. ¶56).
- The essential elements of Claim 1 are:
- A system comprising:
- at least one memory containing a plurality of memory regions; and
- an access management component that:
- compares received authentication data to stored authentication data associated with a memory region;
- facilitates a wipe erase of a memory region when the received data matches the stored data; and
- facilitates creation of a new security record containing a default authentication credential.
U.S. Patent No. 8,239,611 - "Relocating Data in a Memory Device," issued August 7, 2012
Technology Synopsis
This patent, part of the same family as the ’041 Patent, addresses the performance bottleneck in memory controllers by describing a system with two independent processor components. A first processor handles lower-level memory operations (read/write), while a second, local processor performs higher-level maintenance operations (e.g., wear leveling) simultaneously and without using the first processor's resources. (Compl. ¶14; ’611 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶73).
Accused Features
The complaint accuses Seagate’s FireCuda 530, which allegedly contains a multi-processor controller (Phison PS5018-E18) where different processors simultaneously and independently perform read/write operations and wear leveling. (Compl. ¶¶75-76).
U.S. Patent No. 8,694,776 - "Authenticated Memory and Controller Slave," issued April 8, 2014
Technology Synopsis
This patent describes a secure computing architecture where a host component can offload a task to an external memory component. The memory's internal controller performs the operation on a subset of data (e.g., decrypts it) and transmits only the result back to the host, preventing the host from accessing the underlying data itself (e.g., the encryption keys). (Compl. ¶15; ’776 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶87).
Accused Features
The complaint accuses Seagate’s BarraCuda 510 drives supporting the TCG Opal security standard. These drives are alleged to perform on-device decryption and transmit only the decrypted user data to the host, without exposing the encryption keys used for the operation. (Compl. ¶¶88-89).
U.S. Patent No. 9,734,049 - "Relocating Data in a Memory Device," issued August 15, 2017
Technology Synopsis
Also from the "Relocating Data" family, this patent discloses a method using a first processor for low-level memory operations and a second, independent processor for higher-level data management. The second processor determines whether to relocate data based on a criterion (e.g., wear) and then performs the relocation, with both processors operating over a shared bus. (Compl. ¶16; ’049 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶100).
Accused Features
The complaint again targets the Seagate FireCuda 530 and its multi-core Phison controller, alleging that one processor core performs read/write operations while another independently determines and executes wear leveling tasks over the same bus. (Compl. ¶¶102-104).
U.S. Patent No. 9,767,303 - "Authenticated Memory and Controller Slave," issued September 19, 2017
Technology Synopsis
This patent, related to the ’776 Patent, describes a secure memory system where an internal processor authenticates a host device, performs a requested task on secure data, and transmits the result to the host. The architecture is designed to prevent the host device from accessing the secure data itself, including any keys used to access or decrypt it. (Compl. ¶17; ’303 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶117).
Accused Features
The complaint accuses Seagate’s BarraCuda 510 drives with TCG Opal support, alleging they utilize a process to authenticate a host and perform operations on secure data without permitting the host to access that underlying data or associated keys. (Compl. ¶¶118, 120-121).
U.S. Patent No. 11,093,383 - "Relocating Data in a Memory Device," issued August 17, 2021
Technology Synopsis
Another patent from the "Relocating Data" family, it claims a system with a first processor for read/write operations and a second processor for wear leveling operations. The two processors are configured to operate independently of each other while performing their respective tasks on a shared bus. (Compl. ¶18; ’383 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶133).
Accused Features
The complaint targets the Seagate FireCuda 530 and its multi-core controller, alleging that its processors operate independently to perform read/write and wear leveling functions. (Compl. ¶¶135-137).
U.S. Patent No. 11,609,847 - "Relocating Data in a Memory Device," issued March 21, 2023
Technology Synopsis
This patent also describes a dual-processor memory architecture to improve efficiency. It claims a system with a first processor for read/write operations and a second processor for "data relocation" operations, where both operate independently and utilize the same bus. (Compl. ¶19; ’847 Patent, Abstract).
Asserted Claims
The complaint asserts infringement of at least independent Claim 1. (Compl. ¶148).
Accused Features
The complaint again accuses the Seagate FireCuda 530, alleging its multi-processor controller performs wear leveling (a form of data relocation) independently of its read/write operations. (Compl. ¶¶150-152).
III. The Accused Instrumentality
Product Identification
The complaint broadly accuses families of Seagate data storage products, including Seagate BarraCuda, FireCuda, Nytro, and Exos products. It specifically identifies the FireCuda 530 solid-state drive (SSD), the BarraCuda 510 SSD, and the Exos X Series of Self-Encrypting Drives (SEDs) as exemplary infringing products. (Compl. ¶22).
Functionality and Market Context
The accused instrumentalities are commercially available data storage devices. The complaint focuses on specific technical features alleged to map onto the patent claims. The FireCuda 530 is alleged to contain a Phison PS5018-E18 controller with a multi-processor architecture ("Triple Arm Cortex R5 CPU" and "Dual CoXProcessor") that performs wear leveling to manage the NAND flash memory. (Compl. ¶¶37, 41, 76). The Seagate Exos X Series are identified as SEDs that implement a "Locking SP" (Security Provider) to control read/write access and a "cryptographic erase feature" for data removal. (Compl. ¶¶57, 59, 61). The complaint provides a screenshot from Seagate's website showing these products for sale, suggesting their commercial importance. (Compl. p. 4, screenshot).
IV. Analysis of Infringement Allegations
U.S. Patent No. 10,204,041 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| first performing, using a memory controller module within a memory component, the at least one lower level memory operation on the memory component... | The FireCuda 530 contains a controller (Phison PS5018-E18) which is configured to perform read/write operations on its NAND Flash memory. | ¶37 | col. 5:1-4 |
| determining, using a memory manager module...the memory manager module being independent of the memory controller module, to relocate data...based at least in part on a predetermined relocation criterion... | The FireCuda 530 has a memory manager, alleged to be independent of the controller, that determines when to perform wear leveling, a form of data relocation. | ¶41 | col. 2:48-51 |
| second performing, using the memory manager module...moving the data from the at least one memory location to the at least one different memory location, wherein the at least one different memory location is determined to be less worn... | The FireCuda 530 is configured to perform wear leveling, which involves moving data to a less worn page or block of memory. | ¶42 | col. 2:20-23 |
| wherein the first performing is performed at least partially concurrently with, but independently from, the determining... | The complaint alleges on information and belief that the FireCuda 530 is configured to perform read/write operations concurrently with and independently from its determination of when to relocate data. | ¶44 | col. 6:3-7 |
| the memory manager module performs the higher level memory operation on the first bus. | The complaint alleges on information and belief that the FireCuda 530 is configured to perform the wear leveling operation on the first bus. A screenshot from a product manual explains the wear leveling algorithm. (Compl. p. 12, screenshot). | ¶46 | col. 4:5-9 |
U.S. Patent No. 7,979,658 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an access management component that facilitates control of access to the plurality memory regions based in part on a predetermined access criteria... | The Seagate Exos X Series has a "Locking SP" feature which "controls read/write access" to up to 16 data bands on the drive, each with its own password. A manual screenshot describes this "Controlled access" feature. (Compl. p. 17, screenshot). | ¶59 | col. 2:15-19 |
| compares received authentication data...to authentication data associated with a memory region... | The "Locking SP" in the Exos X Series has access gated by "BandMasterX or EraseMaster passwords." | ¶60 | col. 4:40-45 |
| facilitates a wipe erase of a memory region when the received authentication data matches the authentication data associated with the memory region... | The Exos X Series' "Locking SP" utilizes a "cryptographic erase feature" upon authentication with an EraseMaster password. | ¶61 | col. 2:21-25 |
| and facilitates creation of a new security record that contains a default authentication credential. | After a cryptographic erase, the "BandMaster password reverts to the value of the MSID," which the complaint alleges is the default password assigned by Seagate during manufacturing. | ¶62 | col. 4:50-57 |
Identified Points of Contention
- Scope Questions: For the '041 patent family, a central question may be whether a single, multi-core controller chip, as allegedly used in the FireCuda 530, meets the claim limitation of two "independent" modules or processors. The analysis may turn on whether "independent" requires physical separation or if functional independence between cores on the same die is sufficient. For the '658 patent, a key dispute may be whether a "cryptographic erase" (rendering data unreadable by changing an encryption key) falls within the scope of the term "wipe erase of a memory region," which could be construed to require overwriting the physical data.
- Technical Questions: What evidence does the complaint provide that the accused FireCuda 530's read/write operations are performed "partially concurrently with, but independently from" the determination to perform wear leveling, as required by Claim 1 of the '041 Patent? The complaint makes this allegation "upon information and belief," suggesting it may be a point requiring discovery. (Compl. ¶44). The complaint alleges the Manufacturer's Secure ID (MSID) is a "default password," which may be contested if Seagate argues it is a non-changeable factory ID rather than a user-facing default credential. (Compl. ¶62).
V. Key Claim Terms for Construction
Term: "memory manager module being independent of the memory controller module" (’041 Patent, Claim 1)
Context and Importance
This term is central to the claimed dual-processor architecture. The infringement case for the '041 patent family depends on whether the accused single-chip, multi-core controller can be mapped onto this two-module structure. Practitioners may focus on this term because the defendant could argue its integrated controller is a single entity, not two "independent" modules.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The specification suggests functional, rather than necessarily physical, independence, stating the memory manager can be a "separate processor," "part of a memory controller component," or even a "thread on a multithreading memory controller component processor." (’041 Patent, col. 2:50-64).
- Evidence for a Narrower Interpretation: The patent figures consistently depict the "Memory Controller Component" and "Memory Manager Component" as distinct blocks, which may support an argument for structural separation. (’041 Patent, Figs. 1-3). The specification also describes delegating functions "to the memory controller component" and "to the memory manager component," language that may imply separate entities. (’041 Patent, col. 5:1-6).
Term: "wipe erase of a memory region" (’658 Patent, Claim 1)
Context and Importance
The infringement allegation for this element relies on the accused products' "cryptographic erase feature." The definition of "wipe erase" is therefore critical. If the term is construed to require physically overwriting data, the cryptographic erase function may not infringe.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The patent abstract describes the invention as facilitating the "secure removal of information." A cryptographic erase achieves this goal by making the data permanently unreadable. The patent does not explicitly define "wipe erase," which could allow for a broader interpretation consistent with its security objective. (’658 Patent, Abstract).
- Evidence for a Narrower Interpretation: The patent does not mention cryptographic techniques. A party could argue that at the time of the invention, a person of ordinary skill in the art would have understood "wipe erase" to mean overwriting physical memory locations with new data (e.g., zeros or random bits), not merely changing an encryption key while leaving the encrypted data in place.
VI. Other Allegations
Indirect Infringement
The complaint alleges inducement of infringement based on Seagate's affirmative acts of providing instructions, technical support, marketing materials, and product manuals that allegedly guide end-users to use the Accused Products in an infringing manner. (Compl. ¶¶63, 77, 90). The complaint also alleges contributory infringement, stating the accused components are material to the inventions, are not staple articles of commerce, and are known by Seagate to be specially adapted for use in an infringing way. (Compl. ¶¶47, 64, 78).
Willful Infringement
The willfulness allegations are based on alleged pre-suit knowledge. The complaint details a series of notice letters sent by the patents' prior assignee to Seagate beginning on July 27, 2020, which identified the patents and accused products. The complaint alleges that despite this notice, Seagate continued its infringing conduct, supporting a claim for willful infringement. (Compl. ¶¶24-30, 49, 66).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural definition: can the functionally distinct cores within the accused single-chip controller be construed as the claimed "independent" first and second processors or modules, or does the integrated nature of the hardware preclude a finding of infringement for the patents covering dual-processor memory management?
- A key question will be one of technical equivalence: does the accused products' "cryptographic erase" feature, which makes data irrecoverable by discarding an encryption key, meet the claim limitation of a "wipe erase," or is that term limited to the physical overwriting of data?
- A central evidentiary question will concern willfulness: given the detailed pre-suit notice alleged in the complaint, the court will likely examine whether Seagate's continued sales of the accused products after being notified constituted objective recklessness in the face of a substantial and known risk of infringing valid patents.