DCT
2:25-cv-01244
TurboCode LLC v. Fibocom Wireless Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: TurboCode LLC (Texas)
- Defendant: Fibocom Wireless Inc. (People's Republic of China)
- Plaintiff’s Counsel: Direction IP Law
- Case Identification: 2:25-cv-01244, E.D. Tex., 12/22/2025
- Venue Allegations: Plaintiff alleges venue is proper in any U.S. judicial district because the defendant is a foreign corporation not resident in the United States.
- Core Dispute: Plaintiff alleges that Defendant’s 4G/LTE and 5G wireless communication modules infringe a patent related to high-speed turbo decoder architectures.
- Technical Context: Turbo codes are a class of high-performance forward error correction codes integral to modern digital communication standards, such as 4G LTE, used to ensure reliable data transmission over noisy wireless channels.
- Key Procedural History: The patent-in-suit was subject to an Ex Parte Reexamination proceeding initiated in 2006, which concluded in 2009 with the issuance of a Reexamination Certificate. The asserted claim, Claim 6, was amended during this proceeding, indicating it survived scrutiny by the U.S. Patent and Trademark Office against prior art considered at that time.
Case Timeline
| Date | Event |
|---|---|
| 2001-01-02 | U.S. Patent No. 6,813,742 Priority Date |
| 2004-11-02 | U.S. Patent No. 6,813,742 Issue Date |
| 2006-07-13 | Ex Parte Reexamination Request Filed |
| 2009-02-10 | Ex Parte Reexamination Certificate Issued |
| 2025-12-22 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,813,742 - "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture"
- Patent Identification: U.S. Patent No. 6,813,742, "High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture," issued November 2, 2004 (’742 Patent).
The Invention Explained
- Problem Addressed: The patent’s background section states that prior art methods for decoding turbo codes, particularly those using the Maximum a Posteriori (MAP) algorithm, involved high computational complexity with many multiplications and additions. This complexity made implementation in semiconductor (ASIC) devices for consumer mobile communications costly, slow, and power-intensive ('742 Patent, col. 2:48-60).
- The Patented Solution: The invention proposes a decoder architecture using two pipelined and serially concatenated Soft-In/Soft-Out (SISO) Log-MAP decoders. The decoders are connected in a feedback loop via interleaver and de-interleaver memory modules (’742 Patent, col. 2:40-45; Fig. 4). This pipelined structure allows for iterative decoding where one decoder processes data while the other receives processed data from the first, enabling the system to produce a decoded output every clock cycle, thereby increasing data throughput and speed ('742 Patent, col. 2:50-52). The use of the Log-MAP algorithm simplifies the hardware to primarily binary adders, reducing complexity and power consumption ('742 Patent, Abstract).
- Technical Importance: This architectural approach aimed to make high-performance turbo decoding more practical for mass-market 3G mobile devices by improving processing speed and reducing the hardware complexity associated with earlier decoding algorithms ('742 Patent, col. 2:34-40).
Key Claims at a Glance
- The complaint asserts independent claim 6, as amended by the Ex Parte Reexamination Certificate (Compl. ¶13).
- The essential elements of asserted independent claim 6 include:
- A method for iterative decoding of received baseband signals.
- Providing an input buffer with at least three shift registers to receive an input signal and generate first, second, and third shifted input signals.
- Providing first and second soft decision decoders serially coupled in a circular circuit, with each decoder processing soft decision data from the preceding decoder.
- Providing at least one memory module coupled to the output of each decoder, where the output from the second decoder's associated memory module is fed back as an input to the first decoder.
- Processing systematic and extrinsic information data using a MAP probability algorithm or a logarithm approximation thereof.
- Generating a soft decision based on this algorithm.
- Weighing and storing the soft decision information into the corresponding memory module.
- Performing iterative decoding for a predetermined number of times, where the output from the last decoder is fed back to the first decoder in a circular circuit.
- The complaint does not explicitly reserve the right to assert dependent claims (Compl. ¶13).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are various series of wireless modules, including the NL668, L610, L716-EY, L850, FM150, FG132, FG360, and L816-AM series ("Accused Instrumentalities") (Compl. ¶12).
Functionality and Market Context
- The Accused Instrumentalities are alleged to be broadband wireless terminal products that operate on 4G/LTE and 5G cellular networks (Compl. ¶12). The complaint provides product datasheets for several of these modules, confirming their support for various LTE and 5G frequency bands (Compl. pp. 5-12).
- The complaint alleges that these products, by complying with 3GPP standards (Releases 8-13) for 4G/LTE communications, necessarily perform a method of iterative turbo decoding to correct errors in received wireless signals (Compl. ¶¶12, 14). The functionality at issue is the internal architecture and method used by the chipsets within these modules to decode turbo-coded data streams as required by the LTE standard.
IV. Analysis of Infringement Allegations
'742 Patent Infringement Allegations
| Claim Element (from Independent Claim 6) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals; | The Accused Instrumentalities allegedly provide an input buffer that inputs data to the constituent decoders of the turbo decoder and comprises at least three shift registers. A provided diagram shows an "Input Buffer" feeding "SISO Decoders" (Compl. p. 15, Fig. 5). | ¶15 | col. 4:54-61 |
| providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... | The Accused Instrumentalities allegedly provide first and second soft decision decoders connected in series, where each decoder iteratively processes soft information from the other in a looped manner. A provided diagram shows a feedback loop between "SISO 1" and "SISO 2" (Compl. p. 32). | ¶16 | col. 4:9-13 |
| providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder; | The Accused Instrumentalities allegedly include memory modules (e.g., interleavers) coupled to the decoder outputs, with the output of the second decoder's memory module fed back to the first decoder's input. A provided diagram illustrates this parallel architecture with memory feedback (Compl. p. 23, Fig. 3). | ¶17 | col. 4:9-26 |
| processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm; | The Accused Instrumentalities allegedly use at least the BCJR algorithm, a type of MAP algorithm, for turbo decoding in compliance with the 4G LTE standards. | ¶18 | col. 2:41-43 |
| generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm; | The Accused Instrumentalities allegedly generate soft decisions using the MAP/BCJR algorithm to determine the likelihood of a received bit's value. | ¶19 | col. 4:20-21 |
| weighing and storing soft decision information into the corresponding memory module; | The Accused Instrumentalities allegedly weigh (or normalize) and store soft decision information into memory modules like interleavers or de-interleavers as part of the iterative process. | ¶20 | col. 4:40-47 |
| performing, for a predetermined number of times, iterative decoding...wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder...and propagate to the last decoder in a circular circuit. | The Accused Instrumentalities allegedly perform iterative decoding for a set number of iterations, with the output of the second decoder fed back to the first decoder in a circular feedback loop to refine the decoding accuracy. | ¶21 | col. 4:48-49 |
- Identified Points of Contention:
- Scope Questions: The '742 patent was filed in the context of 3G wireless standards. A potential issue is whether the claims, as written, are broad enough to cover the specific turbo decoder implementations used in the 4G/LTE and 5G standards practiced by the Accused Instrumentalities. The complaint's theory relies on the fundamental architectural principles of turbo decoding remaining consistent across these standards.
- Technical Questions: The complaint's infringement allegations are primarily supported by references to public technical standards, academic papers, and general block diagrams, rather than a direct analysis of the Accused Instrumentalities. A central question will be whether the specific, proprietary hardware architecture within Defendant's modules practices each claimed step. For instance, what evidence demonstrates that the accused decoders are "serially coupled" as opposed to a parallel implementation, and that they perform a distinct "weighing" step as required by the claim?
V. Key Claim Terms for Construction
The Term: "soft decision decoders serially coupled in a circular circuit"
- Context and Importance: This term defines the core architecture of the claimed method. Its construction is critical because modern decoder implementations can be highly parallelized. The definition of "serially coupled" and "circular circuit" will determine whether the claim reads on architectures that may differ from the specific pipelined embodiment shown in the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes a functional feedback loop where the output of one decoder becomes the input for the other to enable iterative decoding ('742 Patent, col. 4:9-26). This could support a construction covering any two-decoder architecture that iteratively exchanges information, regardless of the precise hardware arrangement.
- Evidence for a Narrower Interpretation: The patent’s Figure 4 depicts a specific data flow: Decoder A → Interleaver Memory → Decoder B → De-Interleaver Memory → Decoder A. A defendant may argue that "serially coupled in a circular circuit" is limited to this specific pipelined structure, where the decoders operate sequentially on a block of data within a larger iterative loop.
The Term: "weighing and storing soft decision information"
- Context and Importance: This functional step describes how the probabilistic outputs of the decoders are handled. Practitioners may focus on this term because "weighing" could imply a specific mathematical operation, such as normalization, that may or may not be present in the accused system.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term could be interpreted to encompass any processing or modification of the soft decision values (e.g., log-likelihood ratios) before they are stored in memory, a common step in many iterative decoding algorithms.
- Evidence for a Narrower Interpretation: The patent specification does not explicitly define "weighing." A defendant could argue the term requires a specific type of numerical scaling or normalization not present in its implementation, or that the term is indefinite because the patent fails to provide sufficient guidance as to its meaning.
VI. Other Allegations
- Indirect Infringement: The complaint does not contain a separate count for indirect infringement, and it does not allege specific facts, such as instructing others via user manuals, that would support a claim for induced infringement.
- Willful Infringement: The complaint does not contain a count for willful infringement or allege that the defendant had pre-suit knowledge of the ’742 Patent. The allegation of "constructive notice" is generally insufficient to support a claim for willfulness (Compl. ¶23).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary proof: The complaint builds its infringement case on the Accused Instrumentalities' compliance with the 4G/LTE standard. A key question for the court will be whether Plaintiff can successfully bridge the gap between the general requirements of the standard and the specific, proprietary architecture of Defendant's products to show that every element of the asserted method claim is practiced.
- The case will also likely involve a question of architectural scope: Can the claim term "serially coupled in a circular circuit," which describes a specific two-decoder pipelined feedback structure, be construed to cover the potentially more complex and parallelized turbo decoder implementations found in modern 4G and 5G chipsets, or is there a fundamental mismatch in the claimed architecture?