DCT

4:24-cv-00524

TurboCode LLC v. Advantech Co Ltd

Key Events
Complaint
complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 4:24-cv-00524, E.D. Tex., 06/07/2024
  • Venue Allegations: Venue is asserted based on Defendant being a foreign corporation, which under 28 U.S.C. § 1391(c)(3) may be sued in any judicial district. The complaint also alleges that infringing acts occurred within the Eastern District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s industrial computing and communication products that comply with 3G and 4G/LTE cellular standards infringe a patent related to an efficient architecture for a turbo code decoder.
  • Technical Context: The technology involves forward error correction (FEC) using turbo codes, a method essential for ensuring data integrity and achieving high data rates in modern wireless communication systems like 3G and 4G/LTE.
  • Key Procedural History: The patent-in-suit was the subject of an ex parte reexamination, which concluded with the issuance of a Reexamination Certificate. The claim asserted in this litigation was amended during that proceeding, which may strengthen its presumption of validity and will focus the dispute on the newly added language.

Case Timeline

Date Event
1999-05-26 '742 Patent Priority Date
2004-11-02 '742 Patent Issue Date
2006-07-13 '742 Patent Reexamination Request Filed
2009-02-10 '742 Patent Ex Parte Reexamination Certificate Issued
2024-06-07 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

  • Patent Identification: U.S. Patent No. 6,813,742, High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-MAP Decoders Architecture, issued November 2, 2004.
  • The Invention Explained:
    • Problem Addressed: The patent’s background section identifies the high computational complexity of prior art turbo code decoders, particularly those using the Maximum a Posteriori (MAP) algorithm. This complexity, involving numerous multiplications and additions, resulted in slow performance, high power consumption, and costly hardware, making such decoders impractical for power-limited consumer devices like 3G mobile phones (’742 Patent, col. 1:45-61).
    • The Patented Solution: The invention discloses a decoder architecture designed for high-speed, low-power operation. It utilizes two Soft-In/Soft-Out (SISO) decoders operating in a pipelined, iterative loop. This arrangement, depicted in Figure 4, allows one decoder to process data from the other's output via memory modules (interleaver/de-interleaver), enabling the production of a decoded output every clock cycle. The use of Log-MAP decoders further simplifies the hardware by performing calculations in the logarithmic domain, which replaces complex multiplications with simpler additions (’742 Patent, Abstract; col. 2:31-44).
    • Technical Importance: This architectural approach aimed to make high-performance turbo decoding feasible for mass-market, power-constrained 3G wireless devices by increasing data throughput while reducing hardware complexity and cost (’742 Patent, col. 2:31-40).
  • Key Claims at a Glance:
    • The complaint asserts independent method claim 6, as amended by the Ex Parte Reexamination Certificate (Compl. ¶13).
    • The essential elements of asserted claim 6 include:
      • Providing an input buffer with at least three shift registers to generate first, second, and third shifted input signals.
      • Providing first and second soft decision decoders coupled in a circular circuit, where the decoders process specific shifted input signals and the output of the preceding decoder.
      • Providing at least one memory module coupled to the output of each decoder, with the output from the second decoder's associated memory module feeding back to the first decoder's input.
      • Processing systematic and extrinsic information data using a MAP (or logarithmic approximation) algorithm.
      • Generating a soft decision based on that algorithm.
      • Weighing and storing the soft decision information into the memory module.
      • Performing iterative decoding for a predetermined number of times, with a feedback path from the last decoder to the first decoder.
    • The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

  • Product Identification: The accused instrumentalities are a range of Advantech products, including the ICR-3241 series Industrial IoT Routers, TREK-773R-1 Vehicle Mount Terminal, AIM-65/68 series Rugged Tablets, FWA-3034 series Network Appliances, and others (Compl. ¶12).
  • Functionality and Market Context: The complaint identifies these products as industrial-grade computers, routers, and terminals marketed with 4G/LTE connectivity (Compl. pgs. 5-10). The core accused functionality is the products' alleged use of a turbo decoder to process received cellular signals in compliance with 3GPP standards (releases 8-11) (Compl. ¶12, ¶14). The complaint alleges that implementing a turbo decoder is a necessary and inherent function for any device complying with these standards and that all such commercial implementations are recursive and iterative (Compl. ¶17, ¶19).

IV. Analysis of Infringement Allegations

'742 Patent Infringement Allegations

Claim Element (from Independent Claim 6) Alleged Infringing Functionality Complaint Citation Patent Citation
providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals The accused products allegedly use an input buffer structure, such as the "channel coded bit buffer" shown in 3GPP specifications, to receive and provide input signals (e.g., systematic data, parity 1, parity 2) to the decoders. The complaint provides a diagram of an alleged system architecture as evidence. (Compl. ¶18, Fig. 3). ¶20, ¶21, ¶22 col. 4:11-14
providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... The products allegedly perform turbo decoding using two constituent soft-in-soft-out (SISO) decoders arranged in an iterative loop, which the complaint asserts constitutes a "circular circuit." The complaint includes a diagram of a standard turbo decoder to illustrate this alleged structure. (Compl. ¶15, Figure 18). ¶23, ¶25 col. 4:8-14
providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder The accused products' decoders allegedly use interleavers and deinterleavers that function as memory modules. The output from the second decoder is fed back to the first decoder, facilitated by these modules, to enable iterative processing. ¶27, ¶28 col. 4:10-14
processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm The accused products allegedly use the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm, a known MAP algorithm, to process systematic and extrinsic data as required by the 3G/4G standards. ¶30, ¶32 col. 5:15-32
generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm The accused products' use of the BCJR algorithm allegedly generates soft decision outputs, which represent the probability of a decoded bit being a '0' or a '1'. ¶35 col. 5:29-32
weighing and storing soft decision information into the corresponding memory module The accused products allegedly perform "normalization" of soft decision values (e.g., "betaQ" and "alphaQ" variables in source code), which the complaint equates to the claimed "weighing," before storing them in memory modules like the interleaver. ¶36, ¶37 Not specified¹
performing, for a predetermined number of times, iterative decoding from the first to the last of multiple decoders, wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder...and propagate...in a circular circuit The accused products allegedly perform a set number of decoding iterations, as allegedly defined in 3GPP source code by variables like "FEC_ITERATIONS". The iterative process is facilitated by the feedback loop structure, which the complaint equates to a circular circuit. A diagram shows the alleged circular data flow in a turbo decoder. (Compl. ¶23, Figure 18). ¶40, ¶41 col. 4:48-51

¹ The term "weighing" was added during reexamination and does not appear in the original patent specification.

  • Identified Points of Contention:
    • Scope Questions: The complaint's theory appears to equate compliance with the 3G/4G/LTE standard with infringement. A central question for the court will be whether the asserted claim is truly essential to the standard, or if a manufacturer can implement a standards-compliant turbo decoder without practicing every limitation of the claimed method.
    • Technical Questions: A key factual dispute may arise over whether the accused products' input buffering systems meet the specific limitation of an "input buffer comprising at least three shift registers." The complaint alleges this can be met in software, but a defendant may argue their architecture is different (Compl. ¶22). Another question is whether the "normalization" process cited in 3GPP source code constitutes "weighing" as required by the claim (Compl. ¶37).

V. Key Claim Terms for Construction

  • The Term: "weighing"

    • Context and Importance: This term was added to claim 6 during reexamination and is not defined in the specification. Infringement of this element hinges on the complaint's assertion that the "normalization" of soft decision values in standard turbo decoder implementations constitutes "weighing" (Compl. ¶37, ¶39). Practitioners may focus on this term because its construction could be dispositive of infringement.
    • Evidence for a Broader Interpretation: A party could argue that in the context of signal processing, "weighing" should be interpreted broadly to mean any scaling or adjustment of a value's significance, which would include the normalization performed in the log-domain.
    • Evidence for a Narrower Interpretation: The specification provides no explicit support for this term. A party could argue that its plain meaning requires a specific multiplicative operation, which may differ from the log-domain subtraction often used for normalization in the cited algorithms. The prosecution history of the reexamination will be critical evidence.
  • The Term: "circular circuit"

    • Context and Importance: This term describes the coupling of the two decoders. The complaint alleges that the standard feedback loop in a turbo decoder, where the output of the second decoder is returned to the first, meets this limitation (Compl. ¶25).
    • Evidence for a Broader Interpretation: The patent’s block diagrams, such as Figure 4, depict a functional feedback loop rather than a specific hardware circuit. This may support an interpretation where any iterative system with a feedback path from the last processing stage to the first qualifies as a "circular circuit."
    • Evidence for a Narrower Interpretation: A party could argue that the term "circuit" implies a physical hardware arrangement and that a software-implemented iterative process does not qualify. The method claim context may weaken this argument, but the ambiguity of the term could be a focus of dispute.

VI. Other Allegations

  • Indirect Infringement: The complaint does not contain allegations of indirect infringement.
  • Willful Infringement: The complaint does not contain allegations of willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of standards equivalence: does compliance with the 3G/4G/LTE turbo code standard, as alleged by Plaintiff, necessarily require practicing every element of the asserted method claim? The case will likely depend on whether Defendant can demonstrate that its specific, standards-compliant implementation avoids at least one limitation of the claim.
  • A key question of claim construction will be the definition of "weighing", a term added during reexamination. The dispute will center on whether the "normalization" step in standard decoding algorithms falls within the scope of this term, a question whose answer may depend heavily on the reexamination's prosecution history.
  • A central evidentiary question will be one of functional equivalence: do the accused products' software-based buffering and processing functions meet the claim's more structurally-phrased limitations, such as "input buffer comprising at least three shift registers" and "circular circuit"? The court will need to determine if there is a material difference between the functions performed by the accused devices and the specific method steps recited in the claim.