4:24-cv-00791
TurboCode LLC v. Siemens Aktiengesellschaft
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: TurboCode LLC (Texas)
- Defendant: Siemens Industry, Inc. (Delaware)
- Plaintiff’s Counsel: Direction IP Law
- Case Identification: 4:24-cv-00791, E.D. Tex., 10/07/2024
- Venue Allegations: Venue is alleged based on Defendant maintaining a business address in Plano, Texas, and committing alleged acts of infringement within the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s industrial cellular communication products infringe a patent related to turbo code decoder architectures for 3G and 4G/LTE networks.
- Technical Context: The technology concerns methods for efficiently and accurately decoding data in wireless communication systems, a foundational process for enabling high-speed data transmission in cellular networks.
- Key Procedural History: The patent-in-suit underwent Ex Parte Reexamination, with a certificate issuing in 2009, which may strengthen the patent's presumption of validity. The complaint also alleges Defendant had pre-suit knowledge of the patent and infringement based on a letter sent on October 18, 2021.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-26 | U.S. Patent No. 6,813,742 Priority Date |
| 2004-11-02 | U.S. Patent No. 6,813,742 Issue Date |
| 2006-07-13 | Reexamination Request Filed for ’742 Patent |
| 2009-02-10 | Ex Parte Reexamination Certificate Issued for ’742 Patent |
| 2021-10-18 | Plaintiff Sent Pre-Suit Notice Letter to Defendant |
| 2024-10-07 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,813,742 - High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture, issued November 2, 2004
The Invention Explained
- Problem Addressed: The patent addresses the challenge of implementing powerful but computationally intensive decoding algorithms, specifically the Maximum a Posteriori (MAP) algorithm, in power- and cost-sensitive devices like 3G mobile phones. Traditional MAP decoders required complex multiplier circuits that were slow, costly, and consumed significant power, making them impractical for consumer wireless devices (’742 Patent, col. 1:45-61).
- The Patented Solution: The invention proposes a decoder architecture that uses two pipelined Soft-In/Soft-Out (SISO) decoders operating in the "log domain" (Log-MAP). This approach replaces complex multiplications with simpler additions, making the hardware less costly and more power-efficient (’742 Patent, col. 2:51-55). The decoders are serially connected in a feedback loop, allowing for iterative decoding where the output of one decoder refines the input for the next, which improves accuracy in noisy communication environments (’742 Patent, FIG. 4; col. 2:37-50).
- Technical Importance: This architecture provided a more practical path for implementing high-performance turbo codes, which were essential for achieving the high-speed, reliable data rates promised by 3G and subsequent wireless standards (’742 Patent, col. 2:24-29).
Key Claims at a Glance
- The complaint asserts independent claim 6, as amended by the Ex Parte Reexamination Certificate (Compl. ¶12).
- The essential elements of Claim 6 include:
- A method for iteratively decoding received baseband signals.
- Providing an input buffer with at least three shift registers to generate first, second, and third shifted input signals.
- Providing first and second soft decision decoders coupled in a circular circuit, where each decoder processes the output from the preceding one, and where the decoders receive the shifted input signals.
- Providing at least one memory module for each decoder, where the output from the second decoder's memory module is fed back as an input to the first decoder.
- Processing systematic and extrinsic information data using a MAP (or log approximation) algorithm.
- Generating a soft decision based on a MAP (or log approximation) algorithm.
- Weighing and storing the soft decision information into the memory module.
- Performing iterative decoding for a predetermined number of times in a circular circuit.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are a range of Siemens industrial communication products that operate on cellular networks, including CP 1243-7 LTE US, SCALANCE MUM/M series, SIMATIC RTU/S7, RUGGEDCOM RX/RM series, and SITRANS FM MAG 8000 devices (Compl. ¶12).
Functionality and Market Context
The complaint alleges these products are industrial routers, communication processors, and controllers that use 3G and/or 4G/LTE cellular networks for data transmission (Compl. ¶¶ 12, 14). Datasheets included in the complaint show these products are marketed for their 4G/LTE connectivity. A system diagram for the SITRANS FM MAG 8000 shows a wireless communication module transmitting information via a 4G/LTE mobile network (Compl. p. 6). The core of the infringement allegation is that by complying with the 3GPP standards for 3G and 4G/LTE (Releases 8-11), these products necessarily implement a turbo decoder architecture that practices the claimed method (Compl. ¶12). The complaint alleges these products are used for remote monitoring and control in industrial settings (Compl. p. 9).
IV. Analysis of Infringement Allegations
| Claim Element (from Independent Claim 6) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals | The accused products receive an input signal and use a "channel coded bit buffer" that is partitioned to provide three distinct inputs ("soft data," "soft parity 1," "soft parity 2") to the constituent decoders. | ¶20, 21 | col. 9:24-28 |
| providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... | The products implement a turbo decoder with two constituent soft-in/soft-out (SISO) decoders, where the output of the second decoder ("soft output 2") is fed back as an input to the first decoder, forming a circular circuit as depicted in 3GPP standard diagrams. | ¶23, 24 | col. 9:29-43 |
| providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder | The "interleaver" and "deinterleaver" components within the turbo decoder architecture function as the claimed memory modules. The output from the deinterleaver (associated with the second decoder) is fed back to the input of the first decoder. | ¶27, 28 | col. 9:35-40 |
| processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm | The products use the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm, a type of MAP algorithm, to process systematic and extrinsic information as part of the turbo decoding process. | ¶30, 32 | col. 10:35-40 |
| generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm | The BCJR algorithm implemented in the products processes soft input to generate soft decision outputs, which represent the probability of the decoded bits. | ¶35, 38 | col. 10:41-45 |
| weighing and storing soft decision information into the corresponding memory module | Soft decision information is "weighed" through a normalization process (e.g., on "betaQ" and "alphaQ" variables in cited source code) and then stored in memory modules like the interleaver and deinterleaver. | ¶36, 37 | col. 10:46-48 |
| performing, for a predetermined number of times, iterative decoding from the first to the last of multiple decoders... in a circular circuit | Decoding is performed iteratively for a set number of times (e.g., 8, as defined by the "FEC_ITERATIONS" variable in cited source code) via the feedback loop between the first and second decoders. The complaint provides a diagram of a turbo decoder's iterative feedback loop (Compl. p. 18). | ¶40, 41 | col. 10:49-57 |
Identified Points of Contention
- Scope Questions: A central question will be whether the logical constructs and algorithms mandated by the 3G/4G/LTE standards can be read to meet the structural limitations of the patent. For example, does a logically partitioned "channel coded bit buffer" (Compl. p. 20, FIG. 7) described in a standard constitute an "input buffer comprising at least three shift registers" as claimed?
- Technical Questions: The complaint equates the term "weighing," added during reexamination, with the "normalization" of soft decision values shown in 3GPP-related source code (Compl. ¶37). A technical dispute may arise over whether the specific mathematical operation of normalization (a subtraction and comparison) constitutes "weighing" as understood in the context of the patent.
V. Key Claim Terms for Construction
The Term: "input buffer comprising at least three shift registers"
- Context and Importance: This term is critical because the infringement theory relies on mapping it to a logical data structure ("channel coded bit buffer") defined in the 3GPP standards, rather than a specific hardware implementation. The defense may argue that the accused software-based buffers do not meet this structural requirement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's description is largely functional, focused on receiving serial data and producing parallel streams for the decoders. A party could argue that any structure, whether hardware or software, that performs this function meets the limitation's purpose.
- Evidence for a Narrower Interpretation: The term "shift register" has a well-defined meaning in digital logic. The patent's Figure 5 explicitly depicts "N-BIT SHIFT REGISTER" blocks, and the text describes a "Serial-to-parallel (S/P) converter" feeding "three Shift Registers" (’742 Patent, FIG. 5; col. 4:55-58). This may support an argument that the claim requires discrete hardware structures.
The Term: "weighing... soft decision information"
- Context and Importance: This limitation was added during reexamination, making its interpretation pivotal. The complaint's infringement theory hinges on equating "weighing" with the "normalization" of log-likelihood ratio (LLR) values performed in standard turbo decoders.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent itself does not define "weighing." A proponent of a broader view could argue it encompasses any mathematical scaling or adjustment applied to the soft decision values before they are stored, which would include normalization.
- Evidence for a Narrower Interpretation: The reexamination history (not provided in the complaint) would be the primary source here. A party could argue that in the absence of a specific definition, the term should be given its ordinary meaning, which might imply multiplication by a weight factor, and that the accused normalization process (a subtraction and cap) is a different operation.
VI. Other Allegations
Indirect Infringement
The complaint alleges induced infringement, stating that Defendant provides the Accused Instrumentalities to its customers with instructions and advertisements that encourage their use in an infringing manner (i.e., operating on 3G/4G/LTE networks). It is alleged that Defendant knew this use would constitute infringement (Compl. ¶43).
Willful Infringement
Willfulness is alleged based on Defendant’s continued sale of the accused products after receiving a notice letter and claim chart from Plaintiff on October 18, 2021. The complaint claims this put Defendant on notice of an unjustifiably high risk of infringement (Compl. ¶45).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical mapping: do the algorithms and logical data structures mandated by 3G/4G/LTE standards, which are largely implemented in software on modern integrated circuits, meet the more structurally-defined limitations of the 2001-era patent claim, such as the "input buffer comprising at least three shift registers"?
- The case will also turn on claim construction, particularly for the term "weighing" added during reexamination. Will the court find that the "normalization" process cited by the plaintiff from technical standards constitutes "weighing," or will it adopt a narrower definition that creates a non-infringement defense?
- A key evidentiary question will be one of proof: can the plaintiff demonstrate, likely through reverse engineering or expert analysis of the accused products' chipsets and firmware, that the Siemens devices actually practice the specific steps of the claimed method as alleged, beyond merely showing compliance with the 3GPP standards?