DCT

1:19-cv-00977

VLSI Technology LLC v. Intel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:19-cv-00254, W.D. Tex., 04/11/2019
  • Venue Allegations: Venue is asserted based on Defendant maintaining a regular and established place of business in the district and having committed the alleged acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s microprocessors, including the Ivy Bridge and Skylake product families, infringe three patents related to dynamic management of power, voltage, and performance in integrated circuits.
  • Technical Context: The technologies at issue involve methods for optimizing processor power consumption and performance by dynamically scaling cache size, adjusting operating voltages, and managing clock speeds.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of U.S. Patent No. 7,725,759 due to its assertion in a prior lawsuit filed in the District of Delaware on March 1, 2019. For all asserted patents, the complaint alleges willful blindness based on a purported corporate policy at Intel discouraging review of non-Intel patents and on prior litigation involving patents with common inventors.

Case Timeline

Date Event
2005-06-29 U.S. Patent No. 7,725,759 Priority Date
2006-08-30 U.S. Patent No. 7,523,373 Priority Date
2009-01-27 U.S. Patent No. 8,156,357 Priority Date
2009-04-21 U.S. Patent No. 7,523,373 Issue Date
2010-05-25 U.S. Patent No. 7,725,759 Issue Date
2012-04-10 U.S. Patent No. 8,156,357 Issue Date
2019-03-01 Delaware Complaint Filed (re: '759 Patent)
2019-04-11 Complaint Filing Date (W.D. Tex.)

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system"

  • Issued: April 10, 2012 (the “’357 Patent”)

The Invention Explained

  • Problem Addressed: Setting a single minimum operating voltage (Vmin) for a memory high enough to ensure no bits fail is inefficient, as most of the memory could operate at lower voltages. This practice limits opportunities for power savings. (’357 Patent, col. 1:12-26).
  • The Patented Solution: The patent describes a method to dynamically scale the effective size of a memory, such as a multi-way cache, based on the operating voltage. As the supply voltage is lowered, sections of the memory (e.g., cache ways) that become unreliable or non-functional are identified and disabled, while the remaining functional sections continue to be used. (’357 Patent, col. 1:53-66). This allows the processor to operate at lower power levels by using a smaller, but still reliable, portion of the memory.
  • Technical Importance: This approach enables more granular power management in processors, allowing them to achieve lower-voltage states than would be possible if the entire memory array were required to remain fully functional. (’357 Patent, col. 1:21-26).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶15).
  • The essential elements of claim 1 include:
    • A method of using a cache with multiple ways, starting with accessing it at a first power supply voltage.
    • Reducing the voltage to a second, lower value.
    • Identifying a first set of ways as non-functional at this second value by "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage."
    • Accessing the cache at the second voltage, exclusive of the non-functional ways.
    • Increasing the voltage to a third value.
    • Identifying a second set of ways (from the first set) that is now functional at the third value.
    • Accessing the cache including this newly functional second set of ways.
  • The complaint alleges infringement of "one or more claims," which may imply a reservation of the right to assert dependent claims (Compl. ¶14).

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique"

  • Issued: April 21, 2009 (the “’373 Patent”)

The Invention Explained

  • Problem Addressed: The minimum operating voltage varies between different integrated circuits (ICs) due to manufacturing variations. A memory on a chip may also require a higher minimum voltage than the processor core. Designing for a single, worst-case Vmin across all parts is inefficient. (’373 Patent, col. 2:4-8, 2:17-25).
  • The Patented Solution: The invention proposes testing each individual IC to determine its specific minimum memory operating voltage. This value is then permanently stored in a non-volatile location on the chip itself, such as in a fuse or register. (’373 Patent, Abstract). This on-chip data allows the system's power controller to make intelligent decisions based on the actual, measured capabilities of that specific part, rather than a generic specification. (’373 Patent, col. 2:28-37).
  • Technical Importance: This method facilitates part-specific power optimization, allowing each chip to operate closer to its true physical limits for improved power efficiency and performance binning. (’373 Patent, col. 2:25-32).

Key Claims at a Glance

  • The complaint asserts independent claim 16 (Compl. ¶44).
  • The essential elements of claim 16 include:
    • A method involving an integrated circuit with a memory and a separate functional circuit.
    • Testing the memory to determine its minimum operating voltage and storing that value in a non-volatile manner.
    • Providing a first regulated voltage to the functional circuit and a second, higher regulated voltage.
    • Providing the first regulated voltage as the memory's operating voltage when the first voltage is at or above the stored minimum.
    • Providing the second regulated voltage as the memory's operating voltage when the first voltage is below the stored minimum.
  • The complaint alleges infringement of "one or more claims," which may imply a reservation of the right to assert dependent claims (Compl. ¶43).

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device"

  • Issued: May 25, 2010 (the “’759 Patent”)
  • Technology Synopsis: The patent describes a system for managing clock speeds to improve performance. It discloses a method of monitoring multiple "master devices" (e.g., CPU cores) coupled to a bus. When one master device requests a higher clock frequency in response to a change in its own performance or loading, the system provides that higher frequency to a second master device and/or the bus itself. (’759 Patent, Abstract; Compl. ¶¶ 73-74).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶76).
  • Accused Features: The complaint accuses Intel's "Hardware-Controlled Performance States" (HWP) or "Speed Shift" technology, as implemented in Skylake processors. This technology allegedly involves individual cores monitoring their workloads, requesting higher frequencies (P-states) from a central Package Control Unit (PCU), which then applies the new frequency to other cores and the system bus. (Compl. ¶¶ 75, 77, 82).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies "Intel Ivy Bridge processors" and "Intel Skylake processors" as the accused instrumentalities (Compl. ¶¶ 16, 77).

Functionality and Market Context

  • The complaint alleges that Ivy Bridge processors incorporate a "Dynamic Cache Shrink Feature." This feature is alleged to manage power by deactivating a portion of the processor's Last Level Cache "ways" during periods of low activity to enable operation at a lower minimum voltage (VccMin). When high activity is detected, the deactivated ways are brought back online to improve the cache hit rate. (Compl. ¶¶ 17, 22). A provided diagram illustrates this by showing a 16-way cache shrinking to 2 active ways. (Compl. ¶17 at p. 5).
  • The complaint further alleges that Ivy Bridge processors store minimum operating voltage data for various cache configurations in a non-volatile manner and utilize separate power planes for the processor cores and the Last Level Cache (LLC). (Compl. ¶¶ 47, 50). A die shot is provided to show these distinct power planes. (Compl. ¶50 at p. 17).
  • The complaint alleges that Skylake processors use "Hardware-Controlled Performance States" (HWP), also known as "Speed Shift." This technology is described as allowing the processor to autonomously and quickly select its optimal operating frequency and voltage for better performance and power efficiency. (Compl. ¶77). A diagram from a technical presentation is used to allege that a central "Package Control Unit" (PCU) monitors multiple cores connected by a bus and controls their clock frequency. (Compl. ¶79 at p. 26).

IV. Analysis of Infringement Allegations

'357 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
accessing the cache with a power supply voltage applied to the cache at a first value; Intel Ivy Bridge processors operate a cache with a nominal operating voltage. ¶18 col. 6:50-53
reducing the power supply voltage to a second value; The "Dynamic Cache Shrink Feature" reduces the power supply voltage to the cache during low activity workloads. ¶19 col. 6:54-61
identifying a first set of ways ... as being non-functional ... wherein the step of identifying ... comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage; The processor identifies a subset of ways as non-functional at the reduced voltage, allegedly based on stored information that correlates cache size (and active ways) with minimum voltage benefits. A graph is presented to support this correlation. ¶20 col. 4:25-45
accessing the cache exclusive of the first set of ways, wherein the step of accessing the cache exclusive of the first set of ways is performed with the power supply voltage at the second value; The Power Control Unit (PCU) flushes and puts to sleep a subset of the cache ways (e.g., 14 of 16), which are then not accessed. The diagram shows ways 1 and 2 remain active for access. ¶24 col. 7:1-5
increasing the power supply voltage to a third value; identifying a second set of ways ... that is functional ... and accessing the cache including the second set of ways. When high activity is detected, the PCU returns the processor to normal operation by expanding the cache back to the full set of 16 ways, which are functional at the nominal (higher) voltage. ¶26, ¶27 col. 7:42-51

Identified Points of Contention

  • Scope Question: A question for the court may be whether the claim element "retrieving information that correlates non-functional ways" requires a pre-stored lookup table as detailed in the patent's embodiments, or if it can be read broadly enough to cover the alleged algorithmic method where the PCU deactivates a fixed number of ways in response to detecting a "low activity workload."
  • Technical Question: The complaint provides an Intel document referencing "bad cells' or defects" limiting the minimum cache voltage (Compl. ¶21). It raises the question of what evidence connects this phenomenon to the specific infringement theory that lowering the supply voltage causes otherwise functional ways to become non-functional, as required by the claim.

'373 Patent Infringement Allegations

Claim Element (from Independent Claim 16) Alleged Infringing Functionality Complaint Citation Patent Citation
providing an integrated circuit with a memory ... testing the memory to determine ... a minimum operating voltage; storing, in a non-volatile manner, the value of the minimum operating voltage; Intel Ivy Bridge processors allegedly store minimum operating voltages for different cache configurations in a non-volatile manner, making the information accessible after reboots. ¶46, ¶47 col. 2:28-35
providing a functional circuit on the integrated circuit exclusive of the memory; The processor includes cores which are a functional circuit separate from the Last Level Cache (LLC) memory, as shown in the provided die shot. ¶49, ¶50 col. 9:20-22
providing a first regulated voltage to the functional circuit; The processor core (the functional circuit) is powered via a power gate that regulates a "first voltage." ¶51, ¶52 col. 9:22-23
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage; The processor is powered by an off-chip "core power rail," VCC (the second voltage), which is greater than the first voltage when the core's power gate is active. ¶53, ¶54 col. 3:28-29
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage; When the core voltage (first voltage) is high, the power gate is fully open, making the core voltage and VCC (second voltage) the same; this voltage is provided to the memory. ¶55, ¶57 col. 9:24-27
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage... The LLC memory is "ungated" and thus is always provided with VCC (the second voltage). This condition holds when the core voltage (first voltage) is below the minimum. ¶58, ¶59 col. 9:28-34

Identified Points of Contention

  • Scope Question: The claim recites conditionally providing either the first or the second regulated voltage to the memory. The complaint alleges the LLC is "ungated" and "always provided with VCC, the second voltage" (Compl. ¶56). This raises the question of whether the accused system performs the claimed switching of the memory's operating voltage source, or if there is a fundamental mismatch in operation.

V. Key Claim Terms for Construction

'357 Patent

  • Term: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage"
  • Context and Importance: This term defines the mechanism for identifying which cache ways to disable. The infringement analysis may depend on whether Intel's alleged workload-based deactivation meets this limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party may argue the claim language is functional and not limited to a specific structure, covering any method where voltage is an input used to determine which ways are non-functional.
    • Evidence for a Narrower Interpretation: A party may argue the specification's only described embodiment involves pre-characterizing the chip and storing the correlation data in "mapping registers 45" for later lookup, suggesting a more limited scope. (’357 Patent, col. 4:25-45).

'373 Patent

  • Term: "providing the [first/second] regulated voltage as the operating voltage of the memory"
  • Context and Importance: The infringement case for this patent hinges on this term. If the accused LLC is always powered by the second voltage (VCC), the court must decide if it can ever be considered to have the first voltage "provided as the operating voltage."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party may argue that when the first and second voltages are equal, the first voltage is effectively being "provided," regardless of the physical connection to the second voltage rail.
    • Evidence for a Narrower Interpretation: A party may argue that "providing ... as the operating voltage" requires that voltage to be the power source for the memory array. The specification describes VDDmem and VDDlogic as distinct supplies for the memory array and periphery, which may support an interpretation that the memory must be switched to a different power source. (’373 Patent, col. 2:50-58).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents. Inducement allegations are based on Intel providing documentation, datasheets, and developer's manuals that allegedly instruct customers on infringing uses (Compl. ¶¶ 29, 61, 91).
  • Willful Infringement: Willfulness is alleged for all three patents based on knowledge from the date of the complaint's filing. Pre-suit willfulness for all patents is alleged on a theory of willful blindness, based on a purported Intel corporate policy against reading non-Intel patents and prior litigation involving related inventors (Compl. ¶¶ 28, 60, 90). For the ’759 Patent specifically, the complaint alleges pre-suit actual knowledge based on the filing of a prior complaint in Delaware (Compl. ¶90).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim scope: Can the method of "providing" one of two different voltages to a memory, as claimed in the ’373 patent, be construed to read on a system where the memory is allegedly powered by a single, "ungated" voltage rail at all times?
  • A key evidentiary question will be one of functional operation: Does the accused "Dynamic Cache Shrink Feature," which is allegedly triggered by system "workload," operate in the same way as the patented method of "retrieving information that correlates" non-functional cache ways with specific voltage levels, as required by the ’357 patent?
  • A third central question will concern willfulness: Will the allegations of a corporate policy against reviewing patents and prior litigation involving related inventors be sufficient to establish the specific intent required for a finding of willful blindness, particularly for the ’357 and ’373 patents where no prior direct notice is alleged?