DCT

1:24-cv-00697

Eireog Innovations Ltd v. Oracle Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:24-cv-00697, W.D. Tex., 06/24/2024
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant has regular and established places of business in the district and has committed alleged acts of infringement there.
  • Core Dispute: Plaintiff alleges that Defendant’s server products, which incorporate certain Intel and AMD central processing units (CPUs), infringe four patents related to processor interrupt management and cache coherency.
  • Technical Context: The patents address foundational aspects of multi-core processor architecture, specifically methods for managing hardware interrupts in virtualized environments and optimizing cache performance to reduce system-level bottlenecks.
  • Key Procedural History: The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or licensing history related to the Asserted Patents.

Case Timeline

Date Event
2009-05-07 ’399 Patent Priority Date
2010-09-21 ’777 Patent Priority Date
2012-02-14 ’399 Patent Issue Date
2012-08-09 ’626 and ’870 Patents Priority Date
2013-08-06 ’777 Patent Issue Date
2016-09-06 ’626 Patent Issue Date
2016-09-13 ’870 Patent Issue Date
2023-06-22 Oracle Exadata X10M Platform Announced
2024-06-24 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - "Processor interrupt interface with interrupt partitioning and virtualization enhancements," Issued September 6, 2016

The Invention Explained

  • Problem Addressed: In complex data processing systems with multiple processor cores and virtualized environments (partitions), managing and routing hardware interrupts can create performance bottlenecks. Conventional systems often rely on a centralized interrupt controller, and processors must vie for access to it, causing delays, particularly when determining interrupt priority or routing interrupts to the correct software partition (e.g., a specific guest operating system). (’626 Patent, col. 1:11-34).
  • The Patented Solution: The invention describes a processor-based interrupt management system where interrupt-handling logic is moved directly onto the processor core itself. The system uses "special purpose registers" on the core to store partition identifiers and priority levels. When an interrupt arrives, the core can locally and immediately compare the interrupt's partition and priority information against its own registers to determine if the interrupt should be accepted or blocked, without needing to perform a slower, memory-mapped operation to an external controller. (’626 Patent, Abstract; col. 2:16-49). This enables "direct-to-guest" interrupt delivery in a virtualized setting.
  • Technical Importance: This architectural approach aims to reduce interrupt latency and software overhead, which is critical for the performance of virtualized systems, such as cloud computing platforms, that rely on efficient hardware resource sharing. (’626 Patent, col. 2:22-29).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶10).
  • The essential elements of independent claim 1, a method, include:
    • Receiving, at a processor, an interrupt package from an interrupt controller.
    • The package comprises a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
    • Processing the package against one or more partitions running on the processor by comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers at the processor.
    • Determining on a partition basis whether the interrupt request is blocked or forwarded to a targeted thread.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,442,870 - "Interrupt priority management using partition-based priority blocking processor registers," Issued September 13, 2016

The Invention Explained

  • Problem Addressed: Similar to the ’626 Patent, this patent addresses performance degradation in partitioned data processing systems caused by conventional interrupt control mechanisms, which can create access delays and require complex software management (e.g., by a hypervisor) to route interrupts correctly. (’870 Patent, col. 1:12-32).
  • The Patented Solution: The invention discloses a method for managing interrupt priority using dedicated registers on the processor core. It details the use of specific registers, such as an Interrupt Priority Level Register (INTLEVEL) for a hypervisor and a Guest Interrupt Priority Level Register (GINTLEVEL) for a guest operating system. (’870 Patent, col. 2:25-30). An incoming interrupt's priority is compared against the levels stored in these on-core registers to determine whether to block or accept the interrupt, thereby enabling efficient, partition-aware priority blocking at the hardware level. (’870 Patent, Abstract; col. 2:1-20).
  • Technical Importance: By localizing partition-based priority blocking on the processor, the invention aims to simplify interrupt controller design and reduce the system overhead associated with software-based interrupt management in virtualized environments. (’870 Patent, col. 2:5-11).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶20).
  • The essential elements of independent claim 1, a method, include:
    • Receiving at the processor an interrupt package for a first physical interrupt request, the package comprising a first priority value and a first partition identifier.
    • Processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against a stored priority level and partition identifier retrieved from special purpose registers.
    • Determining on a partition basis if the interrupt request is blocked or forwarded.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,504,777 - "Data processor for processing decorated instructions with cache bypass," Issued August 6, 2013

  • Patent Identification: U.S. Patent No. 8,504,777, "Data processor for processing decorated instructions with cache bypass," Issued August 6, 2013. (Compl. ¶28).
  • Technology Synopsis: The patent addresses inefficiencies in performing atomic operations (e.g., read-modify-write) on shared data in memory, which traditionally require slow software locks. (’777 Patent, col. 1:10-25). The solution is a "decorated instruction" that offloads the atomic operation to an "intelligent memory" controller and, to ensure data consistency, explicitly bypasses the processor's cache by invalidating any corresponding cache entry. (’777 Patent, Abstract; col. 2:48-65).
  • Asserted Claims: Independent claim 16 is asserted. (Compl. ¶30).
  • Accused Features: The complaint accuses the cache processing features of products containing Intel CPUs (Skylake-based and newer) and AMD EPYC CPUs. (Compl. ¶29, ¶33).

U.S. Patent No. 8,117,399 - "Processing of coherent and incoherent accesses at a uniform cache," Issued February 14, 2012

  • Patent Identification: U.S. Patent No. 8,117,399, "Processing of coherent and incoherent accesses at a uniform cache," Issued February 14, 2012. (Compl. ¶38).
  • Technology Synopsis: The patent seeks to reduce interconnect traffic from cache coherency "snoops" in multi-core systems. (’399 Patent, col. 1:20-23). It proposes marking cache lines as "coherent" (for data) or "incoherent" (for instructions). A read for an "incoherent" item can be fetched with a limited snoop, reducing traffic. A read for a "coherent" item that hits a cache line marked "incoherent" is treated as a miss, forcing a full snoop to guarantee data integrity. (’399 Patent, Abstract; col. 1:52-col. 2:10).
  • Asserted Claims: Independent claim 14 is asserted. (Compl. ¶40).
  • Accused Features: The complaint accuses the cache processing features of products containing Intel CPUs (Skylake-based and newer) and AMD EPYC CPUs. (Compl. ¶39, ¶43).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the "Accused Products" as a broad category of Oracle's enterprise hardware, including its x86 Servers, Exadata Database Servers (e.g., X9M-2, X10M), and OCI Bare Metal Servers. (Compl. ¶9, ¶19, ¶29, ¶39).

Functionality and Market Context

  • The infringement allegations target the functionality of the underlying CPUs within these Oracle products, specifically Intel CPUs (Haswell, Skylake, and newer architectures) and AMD CPUs (Zen-based architecture). (Compl. ¶9, ¶29).
  • The complaint alleges that these CPUs contain the "interrupt management features" and "cache processing features" that practice the patented inventions. (Compl. ¶13, ¶23, ¶33, ¶43).
  • The complaint alleges these features are integral to the performance of Oracle's high-end server offerings, citing Oracle's own announcements about the Exadata X10M platform. (Compl. ¶12; Ex. 5).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that the Accused Products directly infringe the asserted patents and refers to claim charts attached as exhibits (e.g., Exhibits 2, 3, 10, 11, etc.), which are not included in the complaint document itself. (Compl. ¶10, ¶20). The following summary is based on the narrative infringement theory presented in the complaint.

’626 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
receiving, at the processor, an interrupt package provided by an interrupt controller, where the interrupt package comprises a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier... The complaint alleges that the accused Intel and AMD CPUs, which support virtualization, receive interrupt packages containing information identifying the target partition (e.g., hypervisor or guest OS). ¶8, ¶9 col. 8:31-38
...processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers at the processor... The complaint's theory is that the accused CPUs perform this comparison locally using on-core registers as part of their virtualization and interrupt handling architecture to manage interrupts for different software partitions. ¶8, ¶9 col. 8:38-49
...to determine on a partition basis if the first interrupt request is blocked or forwarded to a targeted thread identified by the thread identifier. The complaint alleges that based on the on-core comparison, the accused CPUs determine whether to block an interrupt or forward it to the appropriate virtualized thread, thereby practicing the claimed partition-based blocking method. ¶8, ¶9 col. 9:1-10

’870 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
receiving at the processor an interrupt package for a first physical interrupt request, where the interrupt package comprises a first priority value and a first partition identifier... The complaint alleges that the accused Intel and AMD CPUs receive interrupts that include priority and partition-identifying information necessary for routing in a virtualized environment. ¶18, ¶19 col. 7:42-47
...processing the interrupt package against one or more partitions running on one or more targeted virtual processors at the processor by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor... The infringement theory alleges that the accused CPUs use on-core registers (such as those for managing Intel VT-x or AMD-V) to store partition-specific priority levels and compare them against incoming interrupts. ¶18, ¶19 col. 7:48-58
...to determine on a partition basis if the first physical interrupt request is blocked or forwarded to a targeted virtual processor. The complaint alleges that this on-core comparison allows the accused CPUs to implement the claimed partition-based priority blocking, deciding whether to service or block an interrupt for a specific partition. ¶18, ¶19 col. 7:59-63

Identified Points of Contention:

  • Scope Questions: A central question for the '626 and '870 patents will be whether the interrupt management architecture in the accused Intel and AMD CPUs (e.g., APIC virtualization, IOMMUs) functions in a way that maps to the claims. The dispute may focus on whether the registers used in the accused CPUs qualify as the "special purpose registers" for partition-based blocking as described in the patents, or if their function is technically distinct.
  • Technical Questions: For the '777 and '399 patents, the dispute will likely concern the specific operation of the accused CPUs' cache systems. It raises the question of whether the complex, multi-state coherency protocols (e.g., MESIF) used in modern CPUs can be said to perform the claimed "cache bypass" or use a state equivalent to "marking... as incoherent" in the manner contemplated by the patents.

V. Key Claim Terms for Construction

Term 1: "special purpose registers at the processor" (’626 Patent, Claim 1; ’870 Patent, Claim 1)

  • Context and Importance: This term is the locus of the invention for the '626 and '870 patents. The claims require that interrupt blocking decisions be made by comparing interrupt data to information stored in these specific on-core registers. Infringement will depend on whether the registers in the accused CPUs that handle interrupt virtualization and prioritization are construed as meeting this definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the function of these registers as storing interrupt context information, such as "interrupt ID, partition ID, thread ID, priority level, and additional interrupt message data." (’626 Patent, col. 2:29-32). A plaintiff may argue any register performing this role qualifies.
    • Evidence for a Narrower Interpretation: The specification provides explicit examples of such registers, including "LPIDR" (Logical Partition ID Register), "INTLEVEL," "EPR" (External Proxy Register), and "EPIDR." (’626 Patent, col. 2:50-58). A defendant may argue the term is limited to registers with these specific, disclosed functions and characteristics.

Term 2: "decorated access instruction with cache bypass" (’777 Patent, Claim 16)

  • Context and Importance: This term defines the core functionality of the asserted claim. The case will likely turn on whether any instructions in the accused CPUs are "decorated" (offloading a read-modify-write operation to memory) and simultaneously cause a "cache bypass" (invalidating the relevant cache line).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes a decorated instruction functionally as one where "the processor determines an instruction operation" and a "decoration value," which are transmitted to a memory device to perform a function, such as modifying a value at a target location. (’777 Patent, col. 2:12-24).
    • Evidence for a Narrower Interpretation: The detailed description states that if a decorated access instruction with cache bypass results in a cache hit, the corresponding entry "is flushed and invalidated." (’777 Patent, col. 2:63-65; Fig. 6, blocks 116, 118). A defendant may argue that the accused CPU instructions do not perform this exact sequence of flushing and invalidating upon a hit.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for all four patents. The stated basis is that Oracle provides customers with "user manuals and online instruction materials on its website" that allegedly instruct and encourage end users to configure and use the Accused Products in a manner that infringes the patents. (Compl. ¶12, ¶22, ¶32, ¶42). The complaint also alleges contributory infringement, stating the accused features are a material part of the invention and not staple articles of commerce. (Compl. ¶13, ¶23, ¶33, ¶43).
  • Willful Infringement: The complaint does not use the term "willful." However, for each patent, it alleges that Oracle has knowledge of the patent and the infringing nature of its products "At least as of the filing and service of this complaint" and continues to infringe. (Compl. ¶12, ¶22, ¶32, ¶42). This forms a basis for alleging post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case will likely depend on the answers to two central questions, one concerning the interrupt management patents and the other concerning the cache management patents.

  • A core issue will be one of technical and functional equivalence: For the '626 and '870 patents, does the sophisticated interrupt virtualization architecture in modern Intel and AMD CPUs operate in the specific manner required by the claims? The court will need to determine if the accused CPUs' use of on-core resources for interrupt handling is equivalent to the claimed "special purpose registers" performing partition-based blocking, or if there is a fundamental mismatch in operation.
  • A second key question will be one of definitional scope and technological evolution: For the '777 and '399 patents, can the claims, which date from 2009-2010, be construed to read on the highly complex and multi-state cache coherency and memory management protocols of modern CPUs? The case will likely require deep expert testimony to determine if concepts like "decorated instruction with cache bypass" and "marking as incoherent" have direct, infringing analogues in the accused technology or if advancements have rendered the patented methods distinct.