DCT

1:25-cv-01036

Advanced Memory Tech LLC v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01036, W.D. Tex., 06/30/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Micron maintains regular and established places of business in the district, including its Micron Storage Solutions Center (“MSSC”) in Austin, and commits acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s DRAM and NAND flash memory modules infringe four patents related to fundamental semiconductor circuit designs for voltage generation, noise reduction, and memory cell operation.
  • Technical Context: The dispute centers on the internal circuitry of DRAM and NAND flash memory, foundational components for a vast range of electronic devices, where efficiency, speed, and physical footprint are critical competitive factors.
  • Key Procedural History: For U.S. Patent No. 7,920,018, the complaint alleges that Micron had pre-suit knowledge of the patent family because an application assigned to Micron cited the parent of the '018 patent as prior art during prosecution. This allegation may form the basis for a claim of willful infringement.

Case Timeline

Date Event
2007-01-17 Earliest Priority Date for '018 Patent
2008-07-09 Earliest Priority Date for '231 Patent
2009-12-03 Earliest Priority Date for '778 Patent
2010-03-04 Micron allegedly identified parent of '018 Patent as prior art
2010-03-10 Earliest Priority Date for '888 Patent
2011-04-05 '018 Patent Issued
2011-06-28 '231 Patent Issued
2011-09-30 Micron allegedly had actual knowledge of '018 Patent family
2011-10-11 Alleged start date of willful infringement for '018 Patent
2013-08-27 '778 Patent Issued
2013-11-26 '888 Patent Issued
2016-01-01 Micron opened its Micron Storage Solutions Center in Austin
2025-06-30 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,920,018 - "Booster Circuit"

  • Patent Identification: U.S. Patent No. 7,920,018, “Booster Circuit,” issued April 5, 2011 (Compl. ¶15).

The Invention Explained

  • Problem Addressed: In conventional booster circuits that use a triple-well structure, connecting the source of a transistor to its N-well creates a parasitic capacitance that must be repeatedly charged and discharged, reducing boost efficiency ('018 Patent, col. 2:21-34). This design also requires separating the N-wells of different transistors, which increases the circuit's physical layout area ('018 Patent, col. 2:34-39).
  • The Patented Solution: The invention proposes a booster circuit with two rows of boosting cells and an analog comparison circuit. This comparison circuit evaluates the input or output potentials of corresponding cells in each row and uses the result to control the N-well potential for multiple cells ('018 Patent, Abstract; col. 2:40-51). By fixing the N-well potential based on the stage's operational state rather than tying it to a changing source voltage, the invention aims to reduce parasitic effects and allow for a more compact layout by sharing a common N-well region ('018 Patent, col. 2:40-51, 5:61-65).
  • Technical Importance: This approach seeks to create more efficient and area-conscious voltage booster circuits, which are essential for the performance and density of semiconductor devices like flash memories (Compl. ¶18).

Key Claims at a Glance

  • The complaint asserts independent Claim 1 (Compl. ¶37).
  • The essential elements of Claim 1 include:
    • A first boosting cell row and a second boosting cell row.
    • At least one analog comparison circuit that outputs a well bias potential, where the potential is generated from input potentials of cells in the first and second rows.
    • Each boosting cell comprising a first well region, a second well region within the first, and a switching element.
    • The switching element is configured to transfer charges between terminals.
    • The well bias potential from the analog comparison circuit is applied to the first well region of the switching element in the boosting cells.
  • The complaint states that its description of infringement is illustrative, suggesting other claims may be asserted later (Compl. ¶38).

U.S. Patent No. 7,969,231 - "Internal Voltage Generating Circuit"

  • Patent Identification: U.S. Patent No. 7,969,231, “Internal Voltage Generating Circuit,” issued June 28, 2011 (Compl. ¶20).

The Invention Explained

  • Problem Addressed: When using a two-stage charge pump system where a second pump generates a higher voltage than the first, the startup time for the second pump can be long. Simply increasing the capacitance of the second pump to speed it up is inefficient and increases the overall circuit area ('231 Patent, col. 4:1-15).
  • The Patented Solution: The patent describes a circuit where a high-current first charge pump is initially used to quickly charge the second, lower-current charge pump to a target voltage ('231 Patent, col. 3:25-34). After this initial boost, the pumps are decoupled. The circuit then uses a frequency dividing circuit and a buffer to supply a slower clock signal to the second charge pump for normal operation, thereby reducing power consumption after the rapid startup phase ('231 Patent, Abstract; col. 4:42-53).
  • Technical Importance: This design allows for a rapid startup of internal voltage generators while maintaining power efficiency and a compact footprint, which are valuable characteristics for memory devices (Compl. ¶22).

Key Claims at a Glance

  • The complaint asserts independent Claims 3 and 6 (Compl. ¶59).
  • The essential elements of Claim 3 include:
    • A first charge pump circuit to generate a second voltage from a first voltage.
    • A second charge pump circuit to generate a third voltage from the second voltage.
    • A frequency dividing circuit to generate a second clock signal by dividing a first clock signal.
    • A buffer circuit to select either the first or second clock signal and generate a third clock signal.
    • The third clock signal is supplied to the second charge pump circuit.
  • The essential elements of Claim 6 include:
    • A first charge pump circuit and a second charge pump circuit.
    • A frequency of a clock signal supplied to the second charge pump is changed in accordance with a control signal.
    • The changed frequency is obtained by dividing an original frequency.

U.S. Patent No. 8,519,778 - "Semiconductor Integrated Circuit and Booster Circuit Including the Same"

  • Patent Identification: U.S. Patent No. 8,519,778, “Semiconductor Integrated Circuit and Booster Circuit Including the Same,” issued August 27, 2013 (Compl. ¶24).
  • Technology Synopsis: The patent addresses the problem of high-frequency noise generated by driver circuits in booster circuits, which can interfere with other components ('778 Patent, col. 1:40-48). The proposed solution is an integrated circuit where a current source is connected in series with the inverters that control the main driver transistors. This current source moderates the rate of voltage change at the inverter output, causing the driver transistors to switch more gradually and thereby reducing high-frequency noise (Compl. ¶26; ’778 Patent, col. 2:19-35).
  • Asserted Claims: Independent Claim 1 (Compl. ¶81).
  • Accused Features: The complaint alleges that the Accused DRAM Modules, including the Micron DDR5 Y52K DRAM devices, contain semiconductor integrated circuits that infringe Claim 1 (Compl. ¶81).

U.S. Patent No. 8,593,888 - "Semiconductor Memory Device"

  • Patent Identification: U.S. Patent No. 8,593,888, “Semiconductor Memory Device,” issued November 26, 2013 (Compl. ¶28).
  • Technology Synopsis: The patent addresses the inefficiency of using two separate regulators—one for a memory cell's drain voltage and another for its gate voltage—which increases circuit area ('888 Patent, col. 2:33-39). The invention discloses a device using a single regulator whose output can be switched. In one mode, the regulator's output controls a voltage-applying transistor to set the drain voltage; in another mode, it is connected directly to the memory cell's gate to set the gate voltage. This dual-purpose use of a single regulator is intended to conserve chip space ('888 Patent, Abstract).
  • Asserted Claims: Independent Claim 1 (Compl. ¶98).
  • Accused Features: The complaint alleges that the Accused DRAM Modules, specifically the Micron DDR5 DRAM Y52K devices, contain semiconductor memory devices that infringe Claim 1 (Compl. ¶98).

III. The Accused Instrumentality

  • Product Identification: The complaint names two broad categories of products: “Accused Flash Memory Modules” and “Accused DRAM Modules” (Compl. ¶¶ 34, 35). Specific exemplar products identified include Micron DRAM LPDDR5X Y52P and DDR5 DRAM Y32A dies for the ’018 Patent, and Micron B47R NAND Flash dies and various DRAM dies (DDR5 Y52K, LPDDR4 Z11M, LPDDR5 Y42M) for the ’231 Patent (Compl. ¶¶ 39, 59).
  • Functionality and Market Context: The accused products are fundamental memory components. The complaint distinguishes between NAND flash (non-volatile memory where data is retained without power) and DRAM (volatile memory that is faster but requires power to retain data) (Compl. ¶¶ 32-33). These modules are sold by Micron and incorporated by its customers into a wide array of end-user electronic products, such as smartphones, servers, and computers (Compl. ¶33). The complaint alleges that Micron is the only U.S.-based manufacturer of memory chips and that DRAM and NAND products constitute the vast majority of its revenue (Compl. ¶5).

IV. Analysis of Infringement Allegations

The complaint provides narrative infringement allegations for each asserted patent. For the lead patents, these allegations are summarized below. No probative visual evidence provided in complaint.

'018 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a first boosting cell row including N stages (N≥1) of the boosting cells; a second boosting cell row including M stages (M≥1) of boosting cells; The accused DRAM products contain a booster circuit comprised of two rows of boosting cells, with each row containing at least one boosting cell. ¶41 col. 11:57-61
at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and an input potential of the boosting cell on the i-th stage (1≦i≦M) of the second boosting cell row, The booster circuit is comprised of at least one analog comparison circuit that outputs a well bias potential generated by an input potential of a boosting cell in each of the two rows. ¶42 col. 11:62-65
wherein: each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element in either or both of the first well region and the second well region, Each boosting cell includes a first well region on a substrate, a second well region in the first well region, and one or more switching elements in these regions. ¶43 col. 12:1-6
the at least one switching element is configured to transfer charges from a first terminal to a second terminal, The switching elements transfer charges from one terminal to another terminal. ¶44 col. 12:7-9
and the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows. The well bias potential of the analog comparison circuit is applied to the first well region of the switching element in the boosting cells of the two rows. ¶45 col. 12:9-14
  • Identified Points of Contention:
    • Technical Question: The complaint's allegations track the claim language without providing specific technical details about the accused products. A central question will be whether the circuitry in Micron’s DRAM dies actually generates a "well bias potential" through a mechanism that compares potentials between two separate cell rows, as required by the claim, or if it uses a different, non-infringing control scheme.
    • Scope Question: The infringement analysis will depend on whether the structures within Micron's products meet the patent's definitions of "boosting cell" and "analog comparison circuit." The court's construction of these terms will be critical.

'231 Patent Infringement Allegations

Claim Element (from Independent Claim 3) Alleged Infringing Functionality Complaint Citation Patent Citation
a first charge pump circuit configured to generate a second voltage from a first voltage; The accused products' internal voltage generating circuit contains a charge pump circuit that generates a second voltage from an initial voltage. ¶63 col. 10:19-21
a second charge pump circuit configured to generate a third voltage from the second voltage; The circuit contains a second charge pump circuit that generates a third voltage from the second voltage. ¶63 col. 10:22-24
a frequency dividing circuit configured to divide a first clock signal to generate a second clock signal; The circuit contains a frequency dividing circuit that divides an initial clock signal to generate a second clock signal. ¶63 col. 10:25-27
and a buffer circuit configured to select the first clock signal or the second clock signal and generate a third clock signal, The circuit contains a buffer circuit that generates a third clock signal from the first or the second clock signal. ¶63 col. 10:28-31
wherein the third clock signal is supplied to the second charge pump circuit. Within the circuit, the third clock signal is supplied to the second charge pump circuit. ¶64 col. 10:32-34
  • Identified Points of Contention:
    • Technical Question: For Claim 3 (asserted against NAND products), the key factual question is whether the accused Micron B47R NAND Flash device actually contains a distinct "frequency dividing circuit" and a "buffer circuit" that selects between different clock signals to drive its charge pump, or if it achieves voltage regulation through a different architecture.
    • Scope Question: For Claim 6 (asserted against DRAM products), the analysis may turn on the meaning of "control signal." What constitutes the "control signal" that changes the clock frequency in the accused DRAMs, and does its function align with the teachings of the patent?

V. Key Claim Terms for Construction

'018 Patent

  • The Term: "analog comparison circuit"
  • Context and Importance: This term is the central feature of Claim 1, distinguishing the invention from prior art that allegedly suffered from inefficiency due to fixed well connections. The infringement case will likely depend on whether the accused Micron products contain a circuit that performs the specific function of this element. Practitioners may focus on this term because it defines the novel control mechanism for the N-well potential.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself is functional, defining the circuit as being "for outputting a well bias potential generated by an input potential...and an input potential..." ('018 Patent, col. 11:62-65). A party may argue this covers any circuit that produces a bias based on two input potentials, regardless of its specific implementation.
    • Evidence for a Narrower Interpretation: The specification's preferred embodiments disclose specific differential amplifier-like structures using N-channel and P-channel transistors (e.g., elements 117-119 and 125 in Fig. 1) to compare voltages and output the "lower" or "higher" of the potentials ('018 Patent, col. 7:30-44). A party may argue the term should be limited to these disclosed structures or their equivalents.

'231 Patent

  • The Term: "frequency dividing circuit"
  • Context and Importance: This element is crucial to Claims 3 and 6, as it embodies the solution of slowing down the clock for the second charge pump to improve efficiency after startup. Whether the accused products infringe will depend on if they contain a structure meeting the definition of this term.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 3 defines the term functionally as "configured to divide a first clock signal to generate a second clock signal" ('231 Patent, col. 10:25-27). A party could argue this encompasses any logic or circuit that produces a clock output with a frequency that is a fraction of an input clock's frequency.
    • Evidence for a Narrower Interpretation: The specification provides a specific example of this circuit: a flip-flop (element 105 in Fig. 2) that produces a clock signal with half the frequency of the input ('231 Patent, Fig. 2; col. 6:1-6). A party could argue that this disclosure limits the term to a dedicated digital logic circuit designed for clock division, as opposed to a more general-purpose control mechanism that might incidentally alter clock timing.

VI. Other Allegations

  • Indirect Infringement: For all four patents, the complaint alleges induced infringement. The stated basis is that Micron encourages its customers to incorporate the accused modules into consumer end-products through its sales, engineering, technical support, and product documentation (e.g., Compl. ¶¶ 48-51, 71, 89, 109).
  • Willful Infringement: The allegations of willfulness differ by patent.
    • '018 Patent: The complaint alleges pre-suit willfulness, stating that Micron had actual knowledge of the patent family since at least September 30, 2011, because a patent application assigned to Micron cited the '018 patent's direct parent as prior art (Compl. ¶54).
    • '231, '778, and '888 Patents: For the remaining patents, the complaint alleges willfulness based on knowledge acquired "since the filing of this complaint," supporting a claim for post-suit willful infringement only (Compl. ¶¶ 78, 95, 115).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central threshold issue will be one of pre-suit knowledge: For the '018 patent, can the plaintiff prove that Micron’s knowledge of a parent patent during its own prosecution legally constitutes knowledge of the asserted divisional patent for the purposes of establishing willful infringement for conduct preceding the lawsuit?
  • The primary evidentiary dispute will likely be one of technical operation: Do the complex voltage management circuits within Micron's memory products function in the specific ways required by the patent claims? For instance, with respect to the '018 patent, does the accused circuit determine well bias via an "analog comparison" of potentials between distinct cell rows, or does it employ a different, non-infringing architecture?
  • The case may also turn on a question of claim scope: Will key terms like "analog comparison circuit" ('018 patent) and "frequency dividing circuit" ('231 patent) be given a broad, functional interpretation, or will the court construe them more narrowly in light of the specific circuit diagrams disclosed in the patent specifications?