DCT

6:19-cv-00254

VLSI Technology LLC v. Intel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:19-cv-00254, W.D. Tex., 04/11/2019
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant Intel Corp maintains a regular and established place of business in the district and has committed the alleged acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Ivy Bridge and Skylake microprocessors infringe patents related to dynamic power management techniques, including voltage-based scaling of cache memory and clock speed control.
  • Technical Context: The technologies at issue concern methods for improving the power efficiency and performance of modern microprocessors, which is a critical design consideration for devices ranging from mobile phones to high-performance servers.
  • Key Procedural History: The complaint alleges that Intel has a corporate policy of forbidding employees from reading non-Intel patents, which it frames as evidence of willful blindness. It also references prior litigation against Intel involving patents assigned to NXP (a predecessor-in-interest to the patents' original assignee) and naming some of the same inventors. For one of the asserted patents, the complaint notes it was previously asserted against Intel in a separate lawsuit filed in the District of Delaware one month prior to this action.

Case Timeline

Date Event
2005-06-29 U.S. Patent No. 7,725,759 Priority Date
2006-08-30 U.S. Patent No. 7,523,373 Priority Date
2009-01-27 U.S. Patent No. 8,156,357 Priority Date
2009-04-21 U.S. Patent No. 7,523,373 Issued
2010-05-25 U.S. Patent No. 7,725,759 Issued
2012-04-10 U.S. Patent No. 8,156,357 Issued
2019-03-01 Prior complaint filed asserting '759 Patent in D. Del.
2019-04-11 Complaint Filed in W.D. Tex.

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system," issued April 10, 2012

The Invention Explained

  • Problem Addressed: The patent addresses the inefficiency that arises when a processor's memory must operate at a fixed minimum voltage (Vmin) that is set high to accommodate worst-case manufacturing variations. This prevents the system from saving power by operating at lower voltages, even when most of the memory could function correctly, leading to a "loss of functionality and/or efficiency" (’357 Patent, col. 1:48-53).
  • The Patented Solution: The invention proposes a method for dynamically scaling the size of a memory, such as a multi-way cache, in response to changes in its supply voltage. As the supply voltage is lowered to save power, the system identifies and deactivates portions of the memory (e.g., specific "ways" of a cache) that become unreliable or "non-functional" at that reduced voltage. The remaining, smaller portion of the memory continues to operate, allowing the system to achieve greater power savings than if the entire memory had to be kept active (’357 Patent, col. 1:53-66).
  • Technical Importance: This approach allows for more aggressive power management in microprocessors by tailoring the active memory size to the available supply voltage, a key technique for improving energy efficiency.

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶15).
  • The essential elements of method claim 1 include:
    • Accessing a cache at a first power supply voltage.
    • Reducing the voltage to a second, lower value.
    • Identifying a first set of cache ways as being non-functional at the second value by "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage."
    • Accessing the cache exclusive of the non-functional ways while at the second voltage.
    • Increasing the voltage to a third value.
    • Identifying a second set of ways from the first set that is now functional at the third value and accessing the cache including this second set.
  • The complaint alleges infringement of "one or more claims" of the patent (Compl. ¶14).

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique," issued April 21, 2009

The Invention Explained

  • Problem Addressed: Due to manufacturing variances, the minimum stable operating voltage for memory can differ significantly from one integrated circuit (IC) to another. A system that uses a single, conservative Vmin for all chips based on a worst-case part may be "unnecessarily giving up the possibility for some parts to be qualified to operate at even lower voltages" (’373 Patent, col. 2:17-27).
  • The Patented Solution: The patent describes a technique where each IC is individually tested during manufacturing to determine its specific minimum memory operating voltage. This unique value is then permanently stored on the chip itself in a non-volatile location, such as a fuse or register. During operation, a controller on the IC can read this stored value to ensure the memory is always supplied with adequate voltage, enabling optimized, part-specific performance (’373 Patent, Abstract; col. 2:28-36).
  • Technical Importance: This method allows for per-chip performance binning, improving manufacturing yields and enabling chips with better characteristics to operate more efficiently, rather than being limited by worst-case parameters.

Key Claims at a Glance

  • The complaint asserts at least independent claim 16 (Compl. ¶44).
  • The essential elements of method claim 16 include:
    • Testing a memory on an IC to determine its minimum operating voltage and storing that value in a non-volatile manner.
    • Providing a "functional circuit" (exclusive of the memory) on the IC.
    • Providing a first regulated voltage to the functional circuit and a second regulated voltage that is greater than the first.
    • Providing the first regulated voltage as the memory's operating voltage when the first voltage is at or above the stored minimum.
    • Providing the second regulated voltage as the memory's operating voltage when the first voltage is below the stored minimum.
  • The complaint alleges infringement of "one or more claims" of the patent (Compl. ¶43).

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device," issued May 25, 2010

  • Technology Synopsis: The patent describes a system for managing performance and power by controlling clock speed. The system monitors multiple "master devices" (e.g., processor cores) coupled to a bus and can selectively increase the clock frequency in response to a request from one of the devices, which may be triggered by a change in its performance or workload (’759 Patent, col. 1:46-52; Abstract). This allows for dynamic adjustment of performance to meet demand.
  • Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶76).
  • Accused Features: The complaint accuses Intel's Skylake processors featuring "Hardware-Controlled Performance States" ("HWP" or "Speed Shift") technology (Compl. ¶75). This technology is alleged to allow the processor to "more quickly select its best operating frequency and voltage for optimal performance and power efficiency" (Compl. ¶77).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses Intel’s "Ivy Bridge" and "Skylake" families of microprocessors (Compl. ¶¶ 16, 45, 77).

Functionality and Market Context

  • The complaint alleges that the accused Ivy Bridge processors incorporate a "Dynamic Cache Shrink Feature." This feature purportedly responds to low processor activity by deactivating a portion of the processor's L3 cache—for example, reducing the active cache ways from 16 to 2—to lower the minimum required supply voltage (VccMin). When high activity is detected, the feature allegedly expands the active cache back to the full 16 ways (Compl. ¶17). The complaint includes a diagram from an Intel presentation illustrating this feature shrinking the active ways from 16 to 2 (Compl. p. 5). The complaint further alleges that these processors store minimum operating voltage values for different cache configurations in a non-volatile manner (Compl. ¶47).
  • The accused Skylake processors are alleged to implement "Hardware-Controlled Performance States (HWP)," also known as "Speed Shift." This technology is described as allowing the processor to autonomously and rapidly select performance states (i.e., operating frequency and voltage) based on the applied workload and hints from the operating system (Compl. ¶¶ 77, 82).
  • These processor families represent major product lines for Intel, and the accused features are central to their power management and performance characteristics.

IV. Analysis of Infringement Allegations

'357 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of using a cache having a plurality of ways... Intel Ivy Bridge processors use a cache organized in 16 ways. A diagram from an Intel presentation illustrates the 16-way organization of the LLC (Last Level Cache) (Compl. p. 5). ¶16, ¶17 col. 2:1-15
accessing the cache with a power supply voltage applied to the cache at a first value; reducing the power supply voltage to a second value; The processor operates at a nominal voltage (first value) and, using the Dynamic Cache Shrink feature, reduces the power supply to a lower voltage (second value) to gain a Vmin benefit. ¶18, ¶19 col. 3:50-56
identifying a first set of ways of the plurality of ways as being non-functional... wherein the step of identifying... comprises: retrieving information that correlates non-functional ways... with values of the power supply voltage; The processor identifies a set of ways that become non-functional at the reduced voltage. This identification is allegedly based on information correlating non-functional ways (e.g., those with "defects") with voltage levels. ¶20, ¶21 col. 4:18-30
accessing the cache exclusive of the first set of ways, wherein the step of accessing the cache exclusive of the first set of ways is performed with the power supply voltage at the second value; The processor, in its low-power state, flushes and puts to sleep a subset of ways (e.g., 14 of 16) and does not access them, operating exclusively with the remaining active ways at the reduced voltage. ¶22, ¶24, ¶25 col. 3:56-60
increasing the power supply voltage to a third value; identifying a second set of ways... that is functional... and accessing the cache including the second set of ways. When the processor detects high activity, it returns to normal operation by increasing the voltage to the nominal level (third value) and expanding back to the full set of 16 ways, which are all functional at that voltage. ¶26, ¶27 col. 4:1-5

Identified Points of Contention

  • Scope Questions: A central question will be whether Intel's "Dynamic Cache Shrink" feature performs the claimed step of "retrieving information that correlates non-functional ways...with values of the power supply voltage." The defense may argue its algorithm for disabling ways to save power is distinct from the patent's described method of using pre-characterized data stored in mapping registers.
  • Technical Questions: The claim requires that the ways be identified as "non-functional" because of the reduced voltage. The complaint alleges the deactivated ways "would be non-functional" (Compl. ¶22), but a key question for the court will be whether the primary reason for deactivation is power savings, or if it is a direct result of the ways becoming operationally unreliable at the lower voltage, as the claim requires.

'373 Patent Infringement Allegations

Claim Element (from Independent Claim 16) Alleged Infringing Functionality Complaint Citation Patent Citation
providing an integrated circuit with a memory... testing the memory to determine... a minimum operating voltage; storing, in a non-volatile manner, the value... Intel Ivy Bridge processors are an integrated circuit with memory. They allegedly test and store the minimum operating voltage for various cache configurations in a non-volatile manner, accessible after reboots. ¶46, ¶47 col. 2:28-36
providing a functional circuit on the integrated circuit exclusive of the memory; The processor includes "cores" (the functional circuit) that are exclusive of the "last level cache (LLC)" memory. A provided diagram shows separate power planes for the Core (green) and LLC (purple) (Compl. p. 17). ¶49, ¶50 col. 5:49-51
providing a first regulated voltage to the functional circuit; The cores (functional circuit) are powered by a "gated" voltage, which is the first regulated voltage. ¶51, ¶52 col. 9:21-23
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage; The processor is powered by a "core power rail," VCC, which is the second regulated voltage. This voltage is greater than the first regulated (gated) voltage when the power gate is active. ¶53, ¶54 col.9:23-24
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage; and When the core voltage (first) is above the memory's minimum, the power gate is fully open, making the first and second voltages equal. The complaint alleges that in this state, the first voltage is provided to the memory array. ¶55, ¶57 col. 9:24-28
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage... The LLC memory is "ungated" and always supplied by the second voltage (VCC). Therefore, when the first voltage drops below the minimum, the second voltage is provided as the operating voltage of the memory. ¶56, ¶58, ¶59 col. 9:28-34

Identified Points of Contention

  • Scope Questions: A significant dispute may arise over the final two "providing" steps. The complaint alleges the LLC memory is "ungated" and thus always receives the "second regulated voltage" (Compl. ¶56). This raises the question of whether the conditions in the claims, which dictate switching between providing the first and second voltages to the memory, are ever met. Does providing a voltage that is always present satisfy the conditional language of the claim?
  • Technical Questions: What is the mechanism by which the "first regulated voltage" is "provided as the operating voltage of the memory"? If the memory is permanently connected to the "second regulated voltage" rail (VCC), the defense may argue the "first regulated voltage" is never its source of operating power, even if the two voltages are momentarily equal. The patent's figures depict a "power supply selector" (’373 Patent, Fig. 1), which suggests an exclusive choice, a detail absent from the complaint's description of the accused product.

V. Key Claim Terms for Construction

'357 Patent: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage"

  • Context and Importance: This term defines the "identifying" step, which is central to the claimed invention. The outcome of the infringement analysis may depend heavily on whether Intel's accused "Dynamic Cache Shrink" algorithm is found to perform this specific action.
  • Intrinsic Evidence for a Broader Interpretation: The patent specification states that minimum operating voltages can be "determined for each part and stored in non-volatile registers on each part" (’357 Patent, col. 4:30-34, referencing a related patent concept). A party could argue this supports a broad interpretation covering any use of pre-stored data, not just a direct table lookup.
  • Intrinsic Evidence for a Narrower Interpretation: The patent’s detailed description and Figure 2 illustrate "mapping registers 45" that explicitly store which ways are enabled at specific, discrete voltage levels (V1, V2, V3, V4) (’357 Patent, Fig. 2; col. 4:42-51). A party may argue that this specific embodiment limits the claim to a direct lookup of pre-defined states, rather than a more complex algorithm.

'373 Patent: "providing [a] regulated voltage as the operating voltage of the memory"

  • Context and Importance: This phrase appears in the final two limitations of claim 16, which form the core of the patented power management logic. Infringement hinges on whether the accused Intel processors "provide" voltages to the memory in the claimed conditional manner. Practitioners may focus on this term because the complaint's allegation that the LLC memory is "ungated" and always powered by the second voltage (Compl. ¶56) creates a potential conflict with the claim's conditional structure.
  • Intrinsic Evidence for a Broader Interpretation: The claim language itself does not explicitly require an exclusive power source. A plaintiff might argue that if a voltage is present and sufficient to operate the memory, it is being "provided as the operating voltage," regardless of other present voltages.
  • Intrinsic Evidence for a Narrower Interpretation: Figure 1 of the patent explicitly shows a "power supply selector 21" that chooses between VDDmem and VDDlogic to supply the memory array (’373 Patent, Fig. 1). A defendant could argue this selector implies that only one voltage is "provided" at a time, and that the claim should be construed to require a similar switching mechanism, which the complaint does not allege is present in the accused products.

VI. Other Allegations

Indirect Infringement

  • The complaint alleges both induced and contributory infringement for all asserted patents. The inducement claims are based on allegations that Intel provides customers with documentation, datasheets, and developer manuals that instruct them on using the accused features, with the specific intent to cause infringement (Compl. ¶¶ 29, 61, 91).

Willful Infringement

  • The complaint makes detailed willfulness allegations. For all patents, it alleges willful blindness based on Intel’s purported corporate policy of forbidding engineers from reading third-party patents to avoid infringement claims. It further supports this by noting prior litigation against Intel involving patents from a predecessor assignee (NXP) and naming some of the same inventors (Compl. ¶¶ 28, 60). For the ’759 Patent, the complaint alleges actual, pre-suit knowledge based on its assertion in a separate lawsuit filed by VLSI against Intel in Delaware approximately one month before the present case (Compl. ¶90).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of functional operation: Does the alleged power delivery architecture of Intel’s Ivy Bridge processors, where the LLC memory is purportedly "ungated" and always powered by a main VCC rail, align with the conditional logic of '373 Patent's claim 16, which describes switching the memory's operating voltage between a first and second regulated source?
  • A second key question will be one of definitional scope: Can the '357 Patent's requirement to identify non-functional cache ways by "retrieving information that correlates" them with voltage values be construed to cover Intel's accused "Dynamic Cache Shrink" algorithm, or is the claim limited to a more direct lookup of pre-characterized data as depicted in the patent's embodiments?
  • Finally, the case will likely involve a significant dispute over knowledge and intent: Will the allegations of Intel's corporate policy against reading patents, combined with a history of litigation involving related inventors and assignees, be sufficient for a finding of willful blindness, and how will the specific notice provided by the earlier Delaware lawsuit affect the willfulness analysis for the '759 Patent?