VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: Mann | Tindel | Thompson; HALEY & OLSON, P.C.
• Case Identification: 6:19-cv-254, W.D. Tex., 04/11/2019
• Venue Allegations: Venue is asserted based on Defendant Intel maintaining a regular and established place of business in the Western District of Texas and having committed acts of infringement within the district.
• Core Dispute: Plaintiff alleges that certain of Defendant’s microprocessors, including those with "Dynamic Cache Shrink" and "Hardware-Controlled Performance States" (HWP) features, infringe patents related to dynamically scaling memory size based on operating voltage and managing clock speeds.
• Technical Context: The technologies at issue concern methods for managing power consumption and performance in modern processors, a critical design area for balancing computational speed with energy efficiency in devices ranging from servers to mobile computers.
• Key Procedural History: The complaint alleges that Intel had pre-suit knowledge of U.S. Patent No. 7,725,759 due to a prior lawsuit filed by VLSI in the District of Delaware on March 1, 2019. For all asserted patents, the complaint also alleges willful blindness based on Intel's purported corporate policy of discouraging engineers from reading third-party patents and on prior litigation involving patents from the same inventors.

Case Timeline

Date	Event
2005-06-29	’759 Patent Priority Date
2006-08-30	’373 Patent Priority Date
2009-01-27	’357 Patent Priority Date
2009-04-21	’373 Patent Issue Date
2010-05-25	’759 Patent Issue Date
2012-04-10	’357 Patent Issue Date
2019-03-01	Prior complaint asserting ’759 Patent filed in D. Del.
2019-04-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system," issued April 10, 2012

The Invention Explained

• Problem Addressed: The patent describes that setting a single, fixed minimum operating voltage (Vmin) for a memory high enough to ensure all bits function correctly is inefficient. This approach prevents the system from operating at lower, more power-efficient voltages, even if only a small fraction of memory bits would fail at those levels (Compl. ¶12; ’357 Patent, col. 1:41-53).
• The Patented Solution: The invention proposes a method to dynamically scale the effective size of a memory based on its supply voltage. As the voltage is reduced, portions of the memory that become unreliable (e.g., specific "ways" in a cache) are identified and disabled. This allows the remaining, smaller, functional portion of the memory to continue operating correctly at the lower voltage, thereby saving power. When the voltage is increased, the previously disabled portions can be re-enabled. (Compl. ¶13; ’357 Patent, col. 1:53-66).
• Technical Importance: This technique enables more granular power management, allowing a processor to achieve greater energy efficiency by operating at lower voltages than would be possible if the entire memory capacity had to be maintained under all conditions (Compl. ¶12-13).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶15).
• Essential elements of claim 1 include:
  • A method of using a cache with multiple ways.
  • Accessing the cache at a first voltage, then reducing the voltage to a second value.
  • Identifying a "first set of ways" as non-functional, caused by the second voltage, by "retrieving information that correlates non-functional ways ... with values of the power supply voltage."
  • Accessing the cache exclusive of this first set of ways while at the second voltage.
  • Increasing the voltage to a third value.
  • Identifying a "second set of ways" from the first set that is now functional at the third value.
  • Accessing the cache including this re-enabled second set of ways.

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique," issued April 21, 2009

The Invention Explained

• Problem Addressed: The patent states that the minimum operating voltage of a memory can vary significantly between different integrated circuits due to manufacturing variations, and this voltage is often higher than that required by the processor core. Relying on a universal, worst-case Vmin for all chips is inefficient. (Compl. ¶41; ’373 Patent, col. 2:4-5, 2:17-21).
• The Patented Solution: The invention describes a method where the specific minimum operating voltage for a memory on a given chip is determined during testing and then stored permanently on that chip in a non-volatile location (e.g., fuses or a register). This stored, part-specific value is then used by the chip's controller to manage its power states, ensuring the memory receives sufficient voltage while allowing other circuits (the "functional circuit") to operate at different, potentially lower, voltages. (Compl. ¶42; ’373 Patent, Abstract).
• Technical Importance: This approach allows for part-specific power optimization, enabling individual chips with more robust memories to operate at lower voltages and save more power than would be possible under a conservative, one-size-fits-all design paradigm (Compl. ¶41).

Key Claims at a Glance

• The complaint asserts independent claim 16 (Compl. ¶44).
• Essential elements of claim 16 include:
  • A method comprising testing a memory on an integrated circuit to determine its minimum operating voltage and storing that value in a non-volatile manner.
  • Providing a "functional circuit" on the IC exclusive of the memory.
  • Providing a "first regulated voltage" to the functional circuit and a "second regulated voltage" that is greater than the first.
  • Providing the first regulated voltage as the memory's operating voltage when the first voltage is at least the value of the stored minimum operating voltage.
  • Providing the second regulated voltage as the memory's operating voltage when the first voltage is less than the stored minimum operating voltage.

Multi-Patent Capsule: U.S. Patent No. 7,725,759

• Patent Identification: U.S. Patent No. 7,725,759, "System and method of managing clock speed in an electronic device," issued May 25, 2010 (Compl. ¶69).
• Technology Synopsis: The patent addresses the need for an improved method of controlling clock frequency to selectively deliver faster clock speeds when required for performance (Compl. ¶73; ’759 Patent, col. 1:22-24). The disclosed solution is a method that involves monitoring multiple "master devices" (e.g., CPU cores) on a bus and, upon receiving a request from a first master device triggered by a change in its performance or load, providing a changed clock frequency to control the clock of a second master device and/or the bus itself (Compl. ¶74, ¶85-87; ’759 Patent, col. 8:1-21).
• Asserted Claims: Independent claim 1 (Compl. ¶76).
• Accused Features: The complaint accuses Intel's "Hardware-Controlled Performance States" (HWP), also known as "Speed Shift," technology found in Skylake and subsequent processors. This feature is alleged to autonomously monitor processor workload and select operating frequencies in a manner that infringes the patent. (Compl. ¶75, ¶77, ¶82).

III. The Accused Instrumentality

Product Identification

• The complaint names Intel processors, specifically identifying the "Ivy Bridge" generation as infringing the ’357 and ’373 patents and the "Skylake" generation as infringing the ’759 patent (Compl. ¶16, ¶45, ¶77). The accused technologies are identified as "dynamic cache shrink," the use of non-volatile memory to store minimum SRAM voltages, and "Hardware-Controlled Performance States (HWP)" / "Speed Shift" (Compl. ¶14, ¶43, ¶75).

Functionality and Market Context

• The complaint alleges that the accused "Dynamic Cache Shrink Feature" in Ivy Bridge processors improves the minimum operating voltage (VccMin) by deactivating portions of the processor's last-level cache during periods of low activity (Compl. ¶17). The complaint includes a diagram from an Intel presentation illustrating the feature shrinking the active cache from 16 ways to 2 ways. (Compl. ¶17, p. 5). For the ’759 patent, the accused "Speed Shift" technology is described as a feature that allows the processor to autonomously select its own operating frequency and voltage for optimal performance and power efficiency, a core function for modern CPUs (Compl. ¶77). These are fundamental power and performance management features in commercially significant generations of Intel processors.

IV. Analysis of Infringement Allegations

’357 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
accessing the cache with a power supply voltage applied to the cache at a first value; reducing the power supply voltage to a second value;	Intel's Ivy Bridge processors operate with a nominal voltage and can reduce the supply voltage using the Dynamic Cache Shrink Feature.	¶18-19	col. 12:40-42
identifying a first set of ways ... as being non-functional ... wherein the step of identifying ... comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage;	The processor identifies ways with "'bad cells' or defects" as non-functional at the reduced voltage. This correlation is shown in a graph of "Vmin Benefit with Cache Size."	¶20-21	col. 12:42-51
accessing the cache exclusive of the first set of ways, wherein the step of accessing the cache exclusive of the first set of ways is performed with the power supply voltage at the second value;	The processor's Power Control Unit (PCU) flushes and "puts to sleep" a subset of ways (e.g., 14 of 16 ways), which are then not accessed during low-activity mode. A diagram shows ways 3-16 being put to sleep.	¶22, ¶25, p. 8	col. 12:52-58
increasing the power supply voltage to a third value; ... identifying a second set of ways ... that is functional ... and accessing the cache including the second set of ways.	When the PCU detects high activity, it returns to normal operation by "expanding active ways back to 16," making all ways functional and accessible at the nominal (third) voltage.	¶26-27	col. 12:59-65

’373 Patent Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
testing the memory to determine ... a minimum operating voltage; storing, in a non-volatile manner, the value of the minimum operating voltage;	Intel Ivy Bridge processors store the minimum operating voltage for different cache configurations in a non-volatile manner, accessible after reboots.	¶46-47	col. 14:48-53
providing a functional circuit on the integrated circuit exclusive of the memory;	The processor cores are the "functional circuit," and are shown in a power plane diagram as distinct from the last-level cache (LLC) memory. The complaint includes a diagram showing the "Core (Gated - Green)" and "LLC (Ungated - Purple)" as separate power planes.	¶49-50, p. 17	col. 14:54-55
providing a first regulated voltage to the functional circuit;	The processor cores are powered by a gated voltage, which is the "first regulated voltage."	¶51-52	col. 14:56-57
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage;	The processor is supplied by a main "core power rail," VCC, which is the "second regulated voltage" and is higher than the gated core voltage during low power states.	¶53-54	col. 14:58-60
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage;	When the core voltage (first voltage) is above the memory's minimum, the power gate is fully open, making the core voltage and VCC (second voltage) the same. Plaintiff alleges this provides the first voltage to the memory array.	¶55, ¶57	col. 14:61-65
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage ...	When the core voltage is below the memory's minimum, the LLC memory array is still provided with the higher VCC (second voltage).	¶58-59	col. 14:66-15:4

Identified Points of Contention

• Scope Questions: For the ’357 patent, a key question will be whether the accused processors "retrieve" information as claimed. The claim language suggests a lookup of pre-correlated data, whereas Intel's process may be a real-time hardware determination. The dispute will center on whether this dynamic process falls within the scope of "retrieving."
• Technical Questions: For the ’373 patent, a primary point of contention will be the mechanism of "providing" different voltages to the memory. The complaint alleges the memory is always powered by the "second regulated voltage" (VCC) (Compl. ¶56). Plaintiff's infringement theory appears to rely on an argument of equivalency—that when the "first regulated voltage" (core voltage) equals the second, it is considered "provided" to the memory (Compl. ¶57). This may be at odds with intrinsic evidence in the ’373 patent, such as figures showing a "power supply selector," which suggests a direct switching mechanism is taught.

V. Key Claim Terms for Construction

'373 Patent: "providing the first regulated voltage as the operating voltage of the memory"

• The Term: "providing the first regulated voltage as the operating voltage of the memory" (and the corresponding limitation for the second voltage).
• Context and Importance: The infringement case for the ’373 patent appears to hinge on this term's construction. The complaint's theory requires this phrase to cover an architecture where the memory is not directly switched to receive the first voltage, but is instead always powered by the second voltage. Practitioners may focus on this term because the plaintiff's infringement theory appears to diverge from the mechanism explicitly shown in the patent's own figures.
• Intrinsic Evidence for a Broader Interpretation: The plaintiff may argue that the claim language does not explicitly require a direct electrical switch, and that if the first voltage (at the core) is functionally equivalent to the voltage at the memory, it is being "provided."
• Intrinsic Evidence for a Narrower Interpretation: The patent's Figure 1 explicitly depicts a "Power Supply Selector" (21) that chooses between two different voltage sources (VDDmem and VDDlogic) to supply the "Memory Array" (22) (’373 Patent, Fig. 1). This figure strongly suggests the invention envisioned an actual switching of the power source to the memory, which could support a narrower construction that the accused products do not meet.

'357 Patent: "retrieving information that correlates"

• The Term: "retrieving information that correlates non-functional ways of the cache with values of the power supply voltage".
• Context and Importance: This term defines how the system identifies which cache ways to disable. The viability of the infringement allegation depends on whether the accused processor's on-the-fly hardware logic for managing cache ways constitutes "retrieving" pre-correlated "information."
• Intrinsic Evidence for a Broader Interpretation: The plaintiff may argue that "information" can be embodied in the hardware logic itself and that the processor's act of determining which ways are unstable at a given voltage is a form of "retrieving" this embedded correlation.
• Intrinsic Evidence for a Narrower Interpretation: The patent specification describes using "mapping registers" to store which ways can be enabled at corresponding voltage values (’357 Patent, col. 4:43-46). A defendant may argue this disclosure limits the claim to systems that perform a more traditional lookup from a stored data structure, rather than a dynamic hardware evaluation.

VI. Other Allegations

Indirect Infringement

• The complaint alleges both induced and contributory infringement for all three patents. Inducement is based on allegations that Intel provides customers with documentation, datasheets, and software developer's manuals that instruct them on using the accused features (Compl. ¶29, ¶61, ¶91).

Willful Infringement

• Willfulness is alleged for all asserted patents. The claims are based on Intel’s knowledge of the patents since at least the filing of the complaint. For the ’759 patent, pre-suit knowledge is alleged from the filing of a prior complaint in Delaware on March 1, 2019 (Compl. ¶90). The complaint further supports its willfulness allegations by asserting a theory of willful blindness, based on Intel's alleged corporate policy forbidding engineers from reading third-party patents and its knowledge of related patents from NXP naming some of the same inventors (Compl. ¶28, ¶60, ¶90).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this dispute may turn on the following central questions:

1. A question of structural infringement: Can the ’373 patent’s claim of selectively "providing" a first or second voltage to a memory be met by the accused Intel architecture, where the memory is allegedly powered by a constant high voltage rail and the "provided" voltage is inferred by its relationship to a separate, gated core voltage? Or does the patent’s specification and its depiction of a "power supply selector" require a direct switching mechanism that is absent in the accused products?
2. A question of definitional scope: Does the ’357 patent’s requirement to "retrieve information that correlates" non-functional cache ways with voltage levels cover a dynamic, hardware-based evaluation, as alleged by the plaintiff? Or is the term limited by the patent's disclosure to a more conventional lookup of data stored in mapping registers?
3. An evidentiary question of intent: Can VLSI meet the high bar for proving willful infringement? This will depend on the evidence of Intel’s state of mind, particularly regarding its conduct after being notified of the patents and the persuasiveness of the "willful blindness" theory based on an alleged corporate policy.