VLSI Technology LLC v. Intel Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: VLSI Technology LLC (Delaware)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: Mann | Tindel | Thompson; Haley & Olson, P.C.
• Case Identification: 6:19-cv-254, W.D. Tex., 04/11/2019
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining a regular and established place of business in the district and committing alleged acts of infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s microprocessors, including its "Ivy Bridge" and "Skylake" product lines, infringe three patents related to dynamic management of power, cache memory, and clock speed in integrated circuits.
• Technical Context: The technology at issue involves power management techniques in microprocessors, which are critical for balancing computational performance with energy efficiency in a wide range of computing devices.
• Key Procedural History: The complaint alleges that Defendant was willfully blind to the asserted patents, citing a corporate policy of forbidding engineers from reading non-Intel patents. It also references prior litigation against Defendant involving patents from the same original assignee (NXP) and inventors to support its willfulness claims. For U.S. Patent No. 7,725,759, the complaint specifically notes a prior infringement action filed against Defendant in the District of Delaware.

Case Timeline

Date	Event
2005-06-29	Priority Date – U.S. Patent No. 7,725,759
2006-08-30	Priority Date – U.S. Patent No. 7,523,373
2009-01-27	Priority Date – U.S. Patent No. 8,156,357
2009-04-21	Issue Date – U.S. Patent No. 7,523,373
2010-05-25	Issue Date – U.S. Patent No. 7,725,759
2012-04-10	Issue Date – U.S. Patent No. 8,156,357
2019-03-01	Prior complaint filed asserting the '759 Patent
2019-04-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,156,357 - "Voltage-based memory size scaling in a data processing system"

• Patent Identification: U.S. Patent No. 8,156,357, “Voltage-based memory size scaling in a data processing system,” issued April 10, 2012.

The Invention Explained

• Problem Addressed: The patent describes a problem in data processing systems where the minimum supply voltage (Vmin) for a memory is set at a fixed, high level to ensure all memory bits function correctly. This approach is inefficient because it prevents the system from operating at lower, power-saving voltages that most of the memory could otherwise tolerate. (Compl. ¶12; ’357 Patent, col. 1:42-53).
• The Patented Solution: The invention discloses a method for dynamically scaling the memory's size in response to changes in its supply voltage (Vmem). As the voltage is reduced, sections of the memory (such as ways in a cache) that can no longer operate reliably are identified and disabled. The system continues to operate with the remaining functional, smaller portion of the memory, thereby saving power. When the voltage is increased, previously disabled sections can be re-enabled. (’357 Patent, col. 1:53-66).
• Technical Importance: This technique allows for more granular and efficient power management by adapting the active memory size to the available supply voltage, a key capability for extending battery life and reducing heat in electronic devices. (Compl. ¶12).

Key Claims at a Glance

• The complaint asserts independent claim 1. (Compl. ¶15).
• Essential elements of claim 1 include:
  • Accessing a cache at a first power supply voltage.
  • Reducing the voltage to a second value.
  • Identifying a first set of ways as non-functional due to the second voltage, where this identification involves retrieving information that correlates non-functional ways with power supply values.
  • Accessing the cache exclusive of the non-functional ways while at the second voltage.
  • Increasing the voltage to a third value.
  • Identifying a second set of ways that become functional at the third value.
  • Accessing the cache including this second set of ways.
• The complaint states its allegations are preliminary and non-limiting, reserving the right to assert other claims. (Compl. ¶15).

U.S. Patent No. 7,523,373 - "Minimum memory operating voltage technique"

• Patent Identification: U.S. Patent No. 7,523,373, “Minimum memory operating voltage technique,” issued April 21, 2009.

The Invention Explained

• Problem Addressed: The patent explains that the minimum operating voltage can vary significantly between different components on a chip (e.g., memory vs. processor) and between different chips of the same design due to manufacturing variations. (Compl. ¶41). Designing for a "worst-case scenario" by setting a single high minimum voltage for all chips is inefficient and prevents individual chips from operating at lower voltages they could safely handle. (’373 Patent, col. 2:17-28).
• The Patented Solution: The patented method involves testing each integrated circuit (IC) individually to determine the actual minimum operating voltage for its memory. This part-specific value is then stored permanently on the IC in a non-volatile location (e.g., fuses or a register). This stored data allows the IC's power controller to make more intelligent decisions, such as supplying the memory with its required minimum voltage while potentially running other circuits at an even lower voltage to save power. (’373 Patent, Abstract; col. 2:28-38).
• Technical Importance: This approach enables part-specific power optimization, a practice known as binning, allowing manufacturers to maximize the power efficiency of each individual chip rather than relying on conservative, one-size-fits-all parameters. (’373 Patent, col. 8:4-11).

Key Claims at a Glance

• The complaint asserts independent claim 16. (Compl. ¶44).
• Essential elements of claim 16 include:
  • Providing an IC with a memory and a separate functional circuit.
  • Testing the memory to determine its minimum operating voltage and storing this value in a non-volatile manner.
  • Providing a first regulated voltage to the functional circuit and a second, higher regulated voltage.
  • Conditionally providing either the first or second regulated voltage as the operating voltage of the memory, depending on whether the first regulated voltage is above or below the stored minimum operating voltage.
• The complaint states its allegations are preliminary and non-limiting, reserving the right to assert other claims. (Compl. ¶44).

U.S. Patent No. 7,725,759 - "System and method of managing clock speed in an electronic device"

• Patent Identification: U.S. Patent No. 7,725,759, "System and method of managing clock speed in an electronic device," issued May 25, 2010. (Compl. ¶69).
• Technology Synopsis: The patent addresses the need for improved control over clock frequency to balance performance and power consumption in electronic devices. (Compl. ¶73). The invention describes a method for managing clock speed by monitoring multiple "master devices" (e.g., processor cores) and increasing the clock frequency in response to a request from a device, where the request is triggered by a predefined change in the device's performance, such as an increased workload. (Compl. ¶¶ 74, 81-82).
• Asserted Claims: The complaint asserts independent claim 1. (Compl. ¶76).
• Accused Features: The complaint accuses Intel's processors featuring "Hardware-Controlled Performance States ('HWP' or 'Speed Shift') technology" of infringement, whereby a Package Control Unit (PCU) monitors processor cores and adjusts operating frequency and voltage in response to workload changes. (Compl. ¶¶ 75, 79, 82).

III. The Accused Instrumentality

Product Identification

• The complaint identifies Intel "Ivy Bridge" processors as infringing the '357 and '373 patents and Intel "Skylake" processors as infringing the '759 patent. (Compl. ¶¶ 16, 45, 77). The complaint notes these are preliminary and non-limiting examples. (Compl. ¶15).

Functionality and Market Context

• The complaint alleges that accused Ivy Bridge processors implement a "Dynamic Cache Shrink Feature." (Compl. ¶17). This feature, controlled by a Power Control Unit (PCU), responds to low processor activity by deactivating a portion of the processor's cache (e.g., shrinking from 16 active ways to 2) to enable operation at a lower minimum voltage. (Compl. ¶¶ 17, 22). When high activity is detected, the deactivated portions of the cache are re-enabled. (Compl. ¶27). The complaint also alleges these processors store minimum operating voltage data for different cache sizes in a non-volatile manner. (Compl. ¶47).
• The complaint alleges that accused Skylake processors implement "Hardware-Controlled Performance States (HWP)" or "Speed Shift" technology, which "delivers dramatically quicker responsiveness... by allowing the processor to more quickly select its best operating frequency and voltage for optimal performance and power efficiency." (Compl. ¶75).
• The complaint does not provide specific allegations regarding the products' commercial importance but identifies them as part of Intel's major "Ivy Bridge" and "Skylake" processor families.

IV. Analysis of Infringement Allegations

’357 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of using a cache having a plurality of ways, comprising:	Intel Ivy Bridge processors operate using a cache organized in 16 ways. A diagram in an Intel presentation depicts this 16-way organization. (Compl. ¶17, p. 5).	¶16	col. 1:53-55
accessing the cache with a power supply voltage applied to the cache at a first value;	The processor operates with a nominal, higher operating voltage during periods of high activity.	¶27	col. 3:56-59
reducing the power supply voltage to a second value;	The "Dynamic Cache Shrink Feature" reduces the power supply to a second, lower voltage to improve VccMin when low activity is detected.	¶19	col. 3:60-61
identifying a first set of ways of the plurality of ways as being non-functional... wherein the step of identifying... comprises: retrieving information that correlates non-functional ways of the cache with values of the power supply voltage;	The processor identifies a subset of ways (e.g., 14 of 16) as non-functional at the reduced voltage by using stored information that correlates cache size (and thus the number of active ways) with minimum operating voltage (Vmin). A graph from an Intel presentation shows this correlation. (Compl. ¶19, p. 6).	¶¶20-21	col. 4:21-25
accessing the cache exclusive of the first set of ways, wherein the step of accessing the cache exclusive of the first set of ways is performed with the power supply voltage at the second value;	The PCU "flushes 14 ways of the cache and puts ways to sleep," and these sleeping ways are not accessed while the processor operates at the reduced voltage.	¶¶22, 25	col. 3:61-64
increasing the power supply voltage to a third value;	When the PCU detects high activity, it "expands active ways back to 16," which involves returning to the nominal, non-reduced operating voltage.	¶27	col. 4:1-3
identifying a second set of ways... that is functional... at the third value; and accessing the cache including the second set of ways.	Upon returning to the nominal voltage, the processor expands operation back to the full set of 16 ways, all of which are alleged to be functional at that voltage and are accessed.	¶27	col. 4:3-6

Identified Points of Contention

• Scope Questions: The claim requires "retrieving information that correlates non-functional ways... with values of the power supply voltage." The complaint points to a graph of Vmin benefit versus cache size. A point of contention may be whether this high-level relationship constitutes the specific "retrieving" of "information that correlates" ways and voltage values as required by the claim.
• Technical Questions: What is the technical basis for identifying ways as "non-functional"? The complaint alleges the processor identifies ways with "defects" that are distributed across the cache. (Compl. ¶21). This raises the question of whether ways are deemed non-functional because of the voltage reduction itself, as the claim requires, or if they are pre-identified defective ways that are managed as part of the power-saving feature.

’373 Patent Infringement Allegations

Claim Element (from Independent Claim 16)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
providing an integrated circuit with a memory that uses an operating voltage;	Intel Ivy Bridge processors are integrated circuits that include a last level cache (LLC) memory.	¶46	col. 9:1-3
testing the memory to determine... a minimum operating voltage; storing, in a non-volatile manner, the value of the minimum operating voltage;	Ivy Bridge processors allegedly "store the minimum operating voltage for different size configurations of the last level cache memory array in a non-volatile manner, accessible after reboots."	¶47	col. 9:4-9
providing a functional circuit on the integrated circuit exclusive of the memory;	The processor includes cores that are separate from the LLC memory. A die shot shows distinct power planes for the "Core (Gated - Green)" and "LLC (Ungated - Purple)." (Compl. ¶50, p. 17).	¶¶49-50	col. 10:20-22
providing a first regulated voltage to the functional circuit;	The cores (the functional circuit) are powered via a power gate that regulates their voltage.	¶52	col. 10:23-24
providing a second regulated voltage, wherein the second regulated voltage is greater than the first regulated voltage;	The processor is supplied by a main "core power rail," VCC (the second voltage), from which the lower core voltage (the first voltage) is derived.	¶¶54, 59	col. 10:25-28
providing the first regulated voltage as the operating voltage of the memory when the first regulated voltage is at least the value of the minimum operating voltage;	When the core voltage (first voltage) is above the memory's minimum operating voltage, the power gate is fully open, making the first and second voltages the same, and this voltage is provided to the memory.	¶57	col. 10:29-33
providing the second regulated voltage as the operating voltage of the memory when the first regulated voltage is less than the value of the minimum operating voltage...	The LLC memory is "ungated" and always supplied with VCC (the second voltage). Therefore, when the core voltage is below the minimum, the LLC is still provided with VCC.	¶¶56, 58-59	col. 10:34-41

Identified Points of Contention

• Technical Questions: The claim recites a conditional method of providing either a first or second voltage to the memory. The complaint alleges the LLC memory is "ungated" and "is always provided with VCC, the second voltage." (Compl. ¶56). This raises a significant question: does the accused product actually perform the claimed conditional switching of the memory's operating voltage, or does the memory operate on a constant voltage (VCC) while the core voltage varies independently?
• Scope Questions: What evidence does the complaint provide for the "testing the memory" step? The infringement theory appears to infer this testing from the subsequent storing of a minimum voltage value, but does not allege direct facts about the testing process itself.

V. Key Claim Terms for Construction

Term: "non-functional" (’357 Patent, Claim 1)

• Context and Importance: The infringement theory for the '357 patent hinges on cache ways becoming "non-functional" at lower voltages. The definition of this term is critical. Practitioners may focus on this term because its construction will determine whether merely unreliable operation is sufficient to infringe, or if complete failure is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states that a "non-functional section of memory indicates a section of memory that may no longer be reliably accessed." (’357 Patent, col. 1:58-60). This language may support a construction where "non-functional" means unreliable, not necessarily completely inoperative.
  • Evidence for a Narrower Interpretation: The specification also refers to preventing "voltage sensitive bits from failing" and sections that "refrain from functional access." (’357 Patent, col. 1:15-16, 56-57). This language could support a stricter interpretation requiring a complete inability to function.

Term: "providing [a voltage] as the operating voltage of the memory" (’373 Patent, Claim 16)

• Context and Importance: This phrase appears in two key limitations that form the core conditional logic of the asserted method claim. The infringement analysis depends on whether the accused product "provides" different voltages to the memory under different conditions in the manner claimed. Practitioners may focus on this term because of the complaint's allegation that the memory's power supply is "ungated."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent does not appear to define a specific mechanism for "providing" the voltage. A party could argue that whichever voltage rail is sourcing the current for the memory array at a given time is the one being "provided as the operating voltage."
  • Evidence for a Narrower Interpretation: The claim structure implies an active switch. A party could argue that "providing" requires a selection mechanism, like the "power supply selector 21" shown in the patent's FIG. 1, which actively switches the memory's power source. The complaint's allegation that the accused LLC is "ungated" and "always provided with VCC" (Compl. ¶56) may support an argument that the condition for "providing the first regulated voltage" is never met.

VI. Other Allegations

Indirect Infringement

• The complaint alleges that Defendant induces infringement by providing customers with documentation, datasheets, and software developer's manuals that instruct on the use of the accused features like "Dynamic Cache Shrink" and "HWP." (Compl. ¶¶ 29, 61, 91). It further alleges contributory infringement, asserting the accused processors are a material part of the inventions and are not staple articles of commerce suitable for substantial noninfringing use. (Compl. ¶¶ 30, 62, 92).

Willful Infringement

• Willfulness is alleged for all three patents based on knowledge from the date of the complaint's filing. (Compl. ¶¶ 28, 60, 90). The complaint also pleads pre-suit willfulness through willful blindness, based on an alleged corporate policy at Intel that forbids employees from reading patents held by outside companies. (Compl. ¶28). For the ’759 Patent, knowledge is also alleged based on a prior complaint filed in Delaware. (Compl. ¶90).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of operational mechanics versus claim language: For the '373 patent, does the accused "ungated" LLC memory, which is allegedly always powered by a single VCC rail, in fact practice the conditional, two-voltage supply method required by claim 16? The resolution will depend on whether the court finds a fundamental mismatch between the accused product's operation and the claimed method.
• A key question of claim construction will likely drive the '357 patent dispute: can the term "non-functional" be construed to mean merely "unreliable," as language in the specification might suggest, or does it require complete operational failure? This distinction appears central to whether the accused "Dynamic Cache Shrink" feature falls within the scope of the claims.
• An evidentiary question will be one of proving an antecedent step: For the '373 patent, which requires "testing the memory to determine" a minimum voltage, the case may depend on what evidence Plaintiff can produce to prove this testing step occurs during Defendant's manufacturing, beyond simply inferring it from the allegation that a resulting value is stored on-chip.