Redstone Logics LLC v. NXP USA Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: NXP Semiconductors N.V. (Netherlands), NXP BV. (Netherlands), and NXP USA, Inc. (Delaware)
  • Plaintiff’s Counsel: Russ August & Kabat
• Case Identification: 7:24-cv-00028, W.D. Tex., 06/17/2024
• Venue Allegations: Plaintiff alleges venue is proper because two defendants are foreign corporations that may be sued in any judicial district, and the third defendant, NXP USA, Inc., has a regular and established place of business within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s i.MX 8 Family Application Processors, which utilize the ARM big.LITTLE architecture, infringe a patent related to managing communication between sets of processor cores that operate with independent power and clock signals.
• Technical Context: The technology concerns power management architectures for multi-core processors, a field critical for balancing computational performance with energy efficiency in modern electronics.
• Key Procedural History: The operative pleading is a First Amended Complaint, filed following an original complaint. No other significant procedural events, such as prior litigation or administrative proceedings involving the patent, are mentioned in the complaint.

Case Timeline

Date	Event
2010-02-26	’339 Patent Priority Date
2013-10-01	’339 Patent Issue Date
2024-06-17	First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - Processor core communication in multi-core processor

• Patent Identification: U.S. Patent No. 8,549,339, Processor core communication in multi-core processor, issued October 1, 2013.

The Invention Explained

• Problem Addressed: The patent addresses the challenge of power management in multi-core processors where all cores conventionally share the same supply voltage and clock signal, which can be inefficient when different cores have vastly different computational loads (’339 Patent, col. 1:5-14).
• The Patented Solution: The invention proposes dividing a multi-core processor into distinct regions or "stripes," where each stripe of cores can operate with its own independent supply voltage and clock signal (’339 Patent, col. 2:20-31). To manage communication between these asynchronous regions, the patent describes an "interface block" that can use components like level shifters to reconcile different voltage levels and synchronizers to align different clock signals, thereby allowing for more granular and efficient power control across the processor (’339 Patent, col. 3:26-47, col. 4:1-12, Figs. 2-3).
• Technical Importance: This architecture enables different sets of processor cores to be optimized for high performance or low power consumption independently, a key strategy for improving overall energy efficiency in complex semiconductor devices (’339 Patent, col. 1:10-14, col. 2:41-44).

Key Claims at a Glance

• The complaint focuses its allegations on independent claim 1, though it alleges infringement of "one or more claims" of the ’339 Patent (Compl. ¶¶ 10, 12).
• The essential elements of independent claim 1 include:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first phase lock loop (PLL).
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL, where the first supply voltage and first clock signal are independent from the second.
  • An interface block coupled between the first and second sets of cores, configured to facilitate communication between them.

III. The Accused Instrumentality

Product Identification

• The Accused Instrumentalities are identified as certain NXP products "comprising two or more sets of processors supporting or based on the ARM big.LITTLE architecture, including without limitation the NXP i.MX 8 Family Application Processors" (Compl. ¶10).

Functionality and Market Context

• The complaint alleges that the accused products infringe by implementing the ARM big.LITTLE architecture (Compl. ¶10). This architecture combines high-performance processor cores ("big" cores) with high-efficiency processor cores ("LITTLE" cores) in a single processor. The operating system can dynamically switch tasks between these different core types to optimize for either performance or power savings.
• The complaint alleges that Defendants make, use, offer for sale, sell, and import these products into the United States (Compl. ¶10).

IV. Analysis of Infringement Allegations

The complaint references a claim chart attached as Exhibit 2, which was not included with the filed complaint document, that purportedly compares independent claim 1 to the Accused Instrumentalities (Compl. ¶12). Based on the complaint's narrative, the infringement theory suggests that the "big" cores in the accused NXP processors constitute the "first set of processor cores" of claim 1, operating with a higher performance and power profile, while the "LITTLE" cores constitute the "second set of processor cores," operating with a lower power profile. The circuitry and logic used to manage communication and task handoffs between these two functionally distinct sets of cores are alleged to be the claimed "interface block" (Compl. ¶10).

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

• The Term: "interface block"

• Context and Importance: This term is central to the claimed invention, as it is the component that enables communication between the otherwise independent sets of cores. The case may turn on whether this term is construed broadly to cover any interconnect between functionally different core clusters (as found in ARM's big.LITTLE architecture) or narrowly to require the specific level-shifter and synchronizer structures detailed in the patent's specification.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Claim 1 itself defines the term functionally as being "configured to facilitate communication between the first set of processor cores and the second set of processor cores," without reciting specific internal components (’339 Patent, col. 8:1-5).
  • Evidence for a Narrower Interpretation: The specification describes specific embodiments, stating an "interface block may have a level shifter" (Fig. 2) or "having a synchronizer" (Fig. 3), which could be argued as defining the scope of the term (’339 Patent, col. 3:31-33; col. 4:5-7).

• The Term: "a first set of processor cores" / "a second set of processor cores"

• Context and Importance: Practitioners may focus on this term because the patent's detailed description primarily illustrates these "sets" as physically arranged "stripes" or "rows" of cores in a grid (’339 Patent, col. 2:23-26, Fig. 1). The accused big.LITTLE architecture, however, groups cores functionally (e.g., high-performance vs. high-efficiency) rather than by physical location. The dispute will question whether a functional grouping meets this claim limitation.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim language uses the general term "set," which does not on its face require a specific physical arrangement. The patent also uses the broader term "region," which could encompass a logical or functional grouping (’339 Patent, col. 8:45-48).
  • Evidence for a Narrower Interpretation: The specification consistently describes the invention with reference to the "stripe" embodiment, where each stripe is a row of processors in a 2-dimensional array, potentially suggesting the invention is limited to such a physical architecture (’339 Patent, col. 2:23-31, Fig. 1).

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement, asserting that Defendants "actively encourage and instruct their customers and end users (for example, through user manuals and online instruction materials on their website) to use the Accused Instrumentalities in ways that directly infringe" (Compl. ¶11). It is also alleged that the products are configured to infringe "out of the box" (Compl. ¶11).
• Willful Infringement: Willfulness is alleged based on post-suit knowledge of the ’339 Patent. The complaint states that "Through at least the filing and service of this Complaint, Defendants have had knowledge of the ’339 Patent," yet allegedly continue their infringing activities (Compl. ¶11). No pre-suit knowledge is alleged.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "interface block", which is described in the patent's embodiments with specific components like level shifters and synchronizers, be construed to cover the standard interconnect fabric used in ARM's big.LITTLE architecture?
• A second key question will be one of structural interpretation: does the claim limitation "a set of processor cores", described in the patent specification primarily as a physical "stripe" or row, read on the functional grouping of cores (high-performance vs. high-efficiency) in the accused NXP processors?
• A central evidentiary challenge will be to establish operational correspondence: Plaintiff must demonstrate through discovery that the accused NXP processors not only use different sets of cores but that they also implement independent, dynamically received supply voltages and clock signals for these sets, and that the communication between them is facilitated in a manner that maps onto the patent's claims.