Redstone Logics LLC v. MediaTek Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: MediaTek, Inc. (Taiwan) and MediaTek USA, Inc. (Delaware)
  • Plaintiff’s Counsel: Russ August & Kabat
• Case Identification: 7:24-cv-00029, W.D. Tex., 01/26/2024
• Venue Allegations: Venue is alleged to be proper for MediaTek, Inc. as a foreign corporation, and for MediaTek USA, Inc. based on its regular and established place of business within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s multi-core processors, which are based on the ARM DynamIQ architecture, infringe a patent related to managing power and communication between different processor core groups.
• Technical Context: The technology concerns dynamic power and clock frequency management in multi-core processors, a critical technique for balancing performance and energy efficiency in modern computing devices.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or specific licensing history related to the patent-in-suit.

Case Timeline

Date	Event
2010-02-26	’339 Patent Priority Date
2013-10-01	’339 Patent Issue Date
2024-01-26	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor" (Issued Oct. 1, 2013)

The Invention Explained

• Problem Addressed: The patent addresses the challenge of power management in conventional multi-core processors, where all processor cores typically share the same supply voltage and clock signal. This monolithic approach simplifies interfaces but limits the ability to finely tune power consumption based on varying computational demands across different cores (’339 Patent, col. 1:7-14).
• The Patented Solution: The invention proposes a multi-core processor architecture divided into distinct regions or "stripes," where each region can receive an independent supply voltage and an independent clock signal (’339 Patent, col. 2:20-31). This allows, for example, a stripe handling high-demand tasks to run at a higher voltage and clock speed, while another stripe with lower demand operates at reduced power levels (’339 Patent, col. 2:51-60). Communication between these asynchronous regions is managed by specialized "interface blocks" that can contain components like level shifters or synchronizers to reconcile the different voltage and clock domains (’339 Patent, Abstract; Fig. 3).
• Technical Importance: This architecture enables more granular dynamic voltage and frequency scaling (DVFS), a foundational technique for improving power efficiency in complex systems-on-a-chip (SoCs) used in mobile devices and servers.

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 and reserves the right to assert other claims (Compl. ¶9, ¶12).
• Independent Claim 1 requires:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first Phase Lock Loop (PLL).
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL.
  • The first supply voltage is independent from the second supply voltage.
  • The first clock signal is independent from the second clock signal.
  • An interface block coupled between the first and second sets of processor cores, configured to facilitate communication between them.

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Instrumentalities" as products comprising two or more sets of processors that support or are based on the DynamIQ Shared Unit architecture (e.g., ARMv8.2, ARMv9, ARMv9.2). The MediaTek Dimensity 9000+ (a.k.a. MT6983) is named as a specific, non-limiting example (Compl. ¶9).

Functionality and Market Context

The complaint alleges that these products are multi-core processors. The infringement theory is predicated on the functionality of the DynamIQ architecture, which allows for the combination of different types of processor cores (e.g., high-performance and high-efficiency) into clusters that can operate at independent voltage and frequency levels (Compl. ¶9). The complaint does not provide further technical detail on the accused products' operation or market position. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references a claim chart in its Exhibit 2, which was not provided with the filed complaint document (Compl. ¶12). The narrative infringement theory, based on the complaint's text, is summarized below.

’339 Patent Infringement Allegations

The complaint alleges that the Accused Instrumentalities, including the MediaTek Dimensity 9000+, directly infringe at least claim 1 of the ’339 Patent (Compl. ¶9, ¶12). The plaintiff's theory appears to map the features of the DynamIQ architecture onto the elements of claim 1. The complaint alleges that these products contain "two or more sets of processors," which corresponds to the claimed "first set" and "second set" of processor cores (Compl. ¶9; ’339 Patent, col. 8:51-61). The core of the allegation is that these sets of processors operate with independent power and clock domains, thus meeting the claim requirements for independent supply voltages and clock signals derived from separate PLLs (Compl. ¶9; ’339 Patent, col. 8:56-65). The complaint implicitly alleges that the hardware connecting these different processor clusters within the DynamIQ architecture functions as the claimed "interface block" that facilitates communication between them (Compl. ¶9; ’339 Patent, col. 8:1-5).

Identified Points of Contention

• Technical Questions: A central question will be whether the specific implementation of the interconnect fabric and communication protocols within the ARM DynamIQ architecture, as used by MediaTek, functions in the manner required by the claimed "interface block." The court may need to examine if it performs the specific functions of facilitating communication between core sets that have independent and dynamically changing voltages and clock signals.
• Scope Questions: The dispute may involve whether the processor "clusters" in the accused DynamIQ architecture (e.g., a cluster of high-performance cores and a cluster of high-efficiency cores) meet the definition of a "first set of processor cores" and a "second set of processor cores" as contemplated by the patent.

V. Key Claim Terms for Construction

• The Term: "an interface block"

• Context and Importance: This term is the structural and functional link between the two otherwise independent sets of processor cores. Its construction will be critical because the infringement analysis depends on mapping the accused product's internal interconnect architecture to this element. Practitioners may focus on this term because its scope will determine whether a generic bus or a more specialized hardware element with specific synchronization capabilities is required.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The claim itself provides a broad functional definition: "configured to facilitate communication between the first set of processor cores and the second set of processor cores" (’339 Patent, col. 8:3-5). This language may support an interpretation covering any hardware that enables data transfer.
  • Evidence for a Narrower Interpretation: The specification discloses specific embodiments of the interface block containing a "level shifter" (to handle different voltage levels) or a "synchronizer" (to handle different clock domains) (’339 Patent, col. 8:7-27; Fig. 2; Fig. 3). This could support a narrower construction requiring one of these specific components or their functional equivalents.

• The Term: "a first set of processor cores" / "a second set of processor cores"

• Context and Importance: The claims require two distinct "sets" of cores. The definition of a "set" is fundamental to the infringement case, as the plaintiff's theory appears to equate ARM's core "clusters" with the patent's "sets." The defense may argue that the accused product is a single, integrated system, not one composed of discrete "sets" in the claimed sense.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent uses the term "regions" and "stripes" interchangeably with the concept of a "set," suggesting a logical or physical grouping of cores that share a power and clock profile (’339 Patent, col. 2:20-26). This could support a broad definition based on shared operational characteristics rather than strict physical separation.
  • Evidence for a Narrower Interpretation: The claims and specification consistently describe the two sets as having independent supply voltages and clock signals, implying a degree of electrical and operational separation that defines the boundary of a "set" (’339 Patent, col. 8:62-65).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b). It asserts that Defendants encourage and instruct their customers and end users to infringe through "engineering documents," "user manuals," and "online instruction materials," and by providing the products in a configuration that performs the claimed method "out of the box" (Compl. ¶10).
• Willful Infringement: The complaint does not use the term "willful infringement." It alleges knowledge of the ’339 Patent and the alleged infringement "Through at least the filing and service of this Complaint," which could form a basis for post-filing enhanced damages but does not allege pre-suit knowledge (Compl. ¶10).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of architectural mapping: Does the accused MediaTek implementation of ARM's DynamIQ architecture, with its distinct clusters of performance and efficiency cores, constitute the "first set" and "second set" of processor cores connected by an "interface block" as those terms are defined in the context of the ’339 patent?
2. A key evidentiary question will be one of functional operation: What evidence will be presented to show that the accused processors "dynamically receive" independent voltage and clock signals for different core sets and that the communication between them is managed in a way that falls within the scope of the patent's claims, as opposed to representing a distinct, non-infringing technical approach to heterogeneous computing?