Redstone Logics LLC v. Qualcomm Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: Qualcomm Inc.; Qualcomm Technologies, Inc. (Delaware)
  • Plaintiff’s Counsel: Russ August & Kabat
• Case Identification: 7:24-cv-00231, W.D. Tex., 09/29/2025
• Venue Allegations: Plaintiff alleges venue is proper based on Defendants having transacted business in the district and maintaining a regular and established place of business in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendants’ multi-core System-on-Chip (SoC) products, such as the Snapdragon series, infringe a patent related to managing communication between processor core groups that operate with independent power and clock signals.
• Technical Context: The patent addresses power management in modern multi-core processors, a critical technology for balancing performance and energy efficiency in devices ranging from smartphones to servers.
• Key Procedural History: The complaint alleges that Defendants had pre-suit knowledge of the patent-in-suit and its alleged infringement due to a prior lawsuit filed by Plaintiff against Samsung, a major customer of Defendants that incorporates the accused Qualcomm products into its own devices.

Case Timeline

Date	Event
2010-02-26	’339 Patent Priority Date
2013-10-01	’339 Patent Issue Date
2023-10-17	Plaintiff files suit against Samsung alleging infringement of the ’339 Patent
2025-09-29	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor"

• Patent Identification: U.S. Patent No. 8,549,339, "Processor core communication in multi-core processor," issued October 1, 2013.

The Invention Explained

• Problem Addressed: In conventional multi-core processors, all cores often share the same supply voltage and clock signal, which simplifies inter-core interfaces but limits power management flexibility. The patent seeks to address the challenges of enabling dynamic voltage and clock speed control for different groups of cores without disrupting communication between them ('339 Patent, col. 1:5-14).
• The Patented Solution: The invention describes a multi-core processor divided into distinct regions or "stripes," where each stripe can receive an independent supply voltage and clock signal. An "interface block" is positioned between these stripes to manage and facilitate communication, ensuring that signals can pass between core groups operating at different voltage levels and/or clock frequencies ('339 Patent, Abstract; col. 2:20-40). This architecture allows tasks with high computational needs to be assigned to a high-power stripe, while less demanding tasks run on a low-power stripe, optimizing overall energy consumption ('339 Patent, col. 2:51-60).
• Technical Importance: This approach enables more granular and efficient dynamic power management (e.g., Dynamic Voltage and Frequency Scaling, or DVFS) in heterogeneous computing environments, a key feature for extending battery life in mobile devices. (Compl. ¶9).

Key Claims at a Glance

• The complaint asserts infringement of at least independent claim 1 (Compl. ¶12).
• Essential elements of claim 1 include:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first clock signal.
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second clock signal, where the voltages and clock signals are independent of the first set's.
  • An interface block coupled to both sets of cores, configured to facilitate communication between them.
• The complaint does not explicitly reserve the right to assert dependent claims, but alleges infringement of "one or more claims" of the ’339 Patent (Compl. ¶9).

III. The Accused Instrumentality

Product Identification

The complaint identifies certain System-on-Chip (SoC) products, including the Snapdragon 8 Gen 2 and Snapdragon 835 Mobile Platform, as the "Accused Instrumentalities" (Compl. ¶9).

Functionality and Market Context

The complaint alleges these SoCs implement architectures like ARM's DynamIQ or big.LITTLE, which feature heterogeneous processor cores organized into different sets or clusters (e.g., high-performance cores and high-efficiency cores) (Compl. ¶9). This architecture, common in modern mobile processors, allows different core clusters to operate at distinct voltages and frequencies to balance performance with power savings. The accused Snapdragon processors are key components in a wide range of high-end mobile devices, underscoring their commercial importance (Compl. ¶9-¶10).

IV. Analysis of Infringement Allegations

The complaint states that a claim chart comparing independent claim 1 of the ’339 Patent to the Accused Instrumentalities is attached as Exhibit 2; however, this exhibit was not provided with the filed complaint (Compl. ¶12). In lieu of a claim chart summary, the narrative infringement theory is as follows:

The complaint alleges that Qualcomm's SoCs, which are based on architectures like DynamIQ or big.LITTLE, directly map onto the structure claimed in the ’339 Patent. The theory suggests that the "first set of processor cores" corresponds to one cluster (e.g., high-performance cores), while the "second set of processor cores" corresponds to another cluster (e.g., high-efficiency cores). It is alleged that these distinct clusters are designed to operate with independent supply voltages and clock signals to manage power consumption, thereby meeting those claim limitations (Compl. ¶9). The complaint implicitly alleges that the interconnect fabric and logic that manage data transfer between these different core clusters constitute the claimed "interface block" configured to facilitate communication. No probative visual evidence provided in complaint.

Identified Points of Contention

• Scope Questions: A central question may be whether the interconnect architecture used in Qualcomm's SoCs constitutes the "interface block" as claimed in the patent. The defense may argue for a narrower construction of this term based on the specific embodiments disclosed in the patent, such as those including "level shifters" or "synchronizers" (’339 Patent, col. 8:6-12, col. 8:21-28).
• Technical Questions: The case may require detailed technical evidence demonstrating how, or if, the accused SoCs' internal logic for managing cross-cluster communication performs the function of the claimed "interface block." The analysis will likely focus on the specific mechanisms that handle voltage level and clock domain differences between the heterogeneous core sets.

V. Key Claim Terms for Construction

• The Term: "interface block"
• Context and Importance: This term is the structural linchpin of claim 1, connecting the two independently powered sets of processor cores. Its construction will be critical, as it will determine whether the complex, integrated interconnect fabrics in modern SoCs fall within the scope of this relatively simple term. Practitioners may focus on this term because its breadth will likely decide the outcome of the infringement analysis.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term itself is generic. Claim 1 defines the block functionally as being "configured to facilitate communication," without specifying any particular internal components or structure ('339 Patent, col. 8:1-5). This may support a broad interpretation covering any hardware that achieves this function between the claimed core sets.
  • Evidence for a Narrower Interpretation: The patent specification discloses specific embodiments of the "interface block" that include components like "level shifters" (Fig. 2) and "synchronizers" (Fig. 3) to handle differences in voltage and clock domains, respectively (’339 Patent, col. 3:26-36; col. 4:1-9). Defendants may argue that these more detailed embodiments limit the scope of the term to structures containing such specific components.

VI. Other Allegations

Indirect Infringement

The complaint alleges inducement of infringement, stating that Qualcomm provides "engineering documents for customers," "user manuals," and "online instruction materials" that encourage and instruct customers and end users to operate the accused SoCs in an infringing manner (Compl. ¶11). It further alleges the products are configured such that users perform the infringing method "out of the box" in their ordinary use (Compl. ¶11).

Willful Infringement

The willfulness allegation is based on alleged pre-suit knowledge. Plaintiff contends that Qualcomm knew of the ’339 Patent and its alleged infringement because of a prior lawsuit Plaintiff filed against Samsung, a major Qualcomm customer that uses the accused Snapdragon 8 Gen 2 processor (Compl. ¶10, ¶15). The complaint posits that, per common industry practice and potential indemnification agreements, Samsung would have provided Qualcomm with notice of the lawsuit and the infringement contentions (Compl. ¶14).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of claim scope: How broadly will the court construe the term "interface block"? Can this term, described with specific examples like level shifters in the patent, be read to cover the proprietary, highly integrated interconnect fabric used to manage communication between heterogeneous core clusters in Qualcomm's modern SoC architectures?
• A central factual question will relate to pre-suit knowledge and willfulness: Can Plaintiff produce sufficient evidence to establish that Qualcomm had actual knowledge of the infringement allegations from the Samsung litigation prior to this suit being filed? The outcome will depend on the nature of the business relationship and any notification or indemnification correspondence between Samsung and Qualcomm.
• A key evidentiary question will be one of technical mapping: Beyond architectural similarities, what specific evidence will Plaintiff present to demonstrate that the internal operations of the accused Snapdragon processors—particularly the handling of signals between different clock and voltage domains—infringe the specific limitations of the asserted claims?