DCT

7:25-cv-00084

TurboCode LLC v. National Instruments Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:

  • Case Identification: 7:25-cv-00084, W.D. Tex., 06/09/2025

  • Venue Allegations: Venue is based on Defendant maintaining a place of business in Austin, Texas, within the Western District of Texas.

  • Core Dispute: Plaintiff alleges that Defendant’s 4G/LTE compliant wireless testing and development products infringe a patent related to high-speed, power-efficient decoder architectures for error correction.

  • Technical Context: The technology at issue is "turbo coding," a high-performance forward error correction method essential for reliable data transmission in modern wireless communication standards like 4G/LTE.

  • Key Procedural History: The patent-in-suit, U.S. Patent No. 6,813,742, underwent an Ex Parte Reexamination, concluding with the issuance of a Reexamination Certificate on February 10, 2009. The asserted claim originates from this reexamination proceeding, indicating that its validity was reviewed and confirmed by the USPTO over prior art presented during that process.

Case Timeline

Date Event
2001-01-02 U.S. Patent No. 6,813,742 Priority Date (Filing Date)
2004-11-02 U.S. Patent No. 6,813,742 Issued
2006-07-13 Reexamination Request Filed for '742 Patent
2009-02-10 '742 Patent Reexamination Certificate Issued
2016-02-22 NI Announces Accused LTE-U/LAA Testbed
2025-06-09 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,813,742 - High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture

  • Patent Identification: U.S. Patent No. 6,813,742, High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture, issued November 2, 2004 (the "'742 Patent"). The complaint asserts Claim 6 from the Ex Parte Reexamination Certificate US 6,813,742 C1. (Compl. ¶¶9, 12).

The Invention Explained

  • Problem Addressed: The patent's background describes that while powerful error correction methods like the Maximum a Posteriori (MAP) algorithm were known, their high computational complexity, requiring many multiplications and additions, made them costly, power-intensive, and slow. This rendered them impractical for implementation in mass-market, power-limited 3G wireless devices. (’742 Patent, col. 1:45-61).
  • The Patented Solution: The invention proposes a decoder architecture that uses two serially connected "Log-MAP" decoders operating in a pipelined fashion. Performing the calculations in the logarithmic domain replaces complex multiplications with simpler additions, making the decoder more suitable for efficient hardware (ASIC) implementation. (’742 Patent, Abstract). The pipelined structure, where one decoder processes data from a memory module while the second processes data from another, is designed to produce a decoded output every clock cycle, thereby increasing data throughput. (’742 Patent, col. 2:35-51).
  • Technical Importance: This architecture was intended to make high-performance turbo decoding feasible for consumer mobile devices by improving speed while reducing hardware complexity and power consumption. (’742 Patent, col. 2:52-62).

Key Claims at a Glance

  • The complaint asserts independent claim 6 of the ’742 Patent. (Compl. ¶12).
  • Claim 6 recites a method with the following essential elements:
    • Providing an input buffer comprising at least three shift registers for receiving and generating shifted input signals.
    • Providing first and second soft decision decoders serially coupled in a circular circuit, where each decoder processes soft decision data from the preceding decoder.
    • Providing at least one memory module coupled to the output of each decoder, where the output of the second decoder's memory module is fed back to the first decoder's input.
    • Processing systematic and extrinsic information data using a maximum a posteriori (MAP) or equivalent logarithm approximation algorithm.
    • Generating a soft decision based on that algorithm.
    • Weighing and storing the soft decision information into the corresponding memory module.
    • Performing iterative decoding for a predetermined number of times, where the output from the last decoder is fed back as an input to the first decoder in a circular circuit.
  • The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are National Instruments products that comply with 4G/LTE standards, including software such as RFmx LTE/LTE-Advanced and RFmx NB-IoT/eMTC, and hardware such as the LTE-U/LAA Testbed, PXIe-series transceivers, and the USRP-2974 Software Defined Radio. (Compl. ¶12). A screenshot from Defendant's website shows the user interface for the RFmx LTE/LTE-Advanced software, described as providing signal generation and analysis for cellular test applications. (Compl. p. 5).

Functionality and Market Context

  • The accused products are used for designing, testing, and analyzing cellular wireless communications systems. (Compl. ¶12). The complaint alleges these products perform iterative decoding of wireless signals in compliance with 4G/LTE standards, which mandate the use of turbo coding. (Compl. ¶¶14, 17).
  • Specifically, the complaint alleges that Defendant's technical documentation describes a Turbo Decoder implementation based on the Max-Log-MAP algorithm, a type of soft decision decoding algorithm, for its LTE applications. (Compl. ¶15).

IV. Analysis of Infringement Allegations

'742 Patent Infringement Allegations

Claim Element (from Independent Claim 6) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of iteratively decoding a plurality of sequences of received baseband signals, the method comprising: providing an input buffer comprising at least three shift registers, for receiving an input signal and generating first, second, and third shifted input signals; The complaint alleges Defendant's documentation describes a "Softbit Input Buffer" that stores systematic and parity bits to support the iterative process. (Compl. ¶¶19, 23). ¶19, ¶23 col. 4:11-14
providing first and second soft decision decoders serially coupled in a circular circuit, wherein each decoder processes soft decision from the preceding decoder output data... The complaint alleges that although NI's documentation describes a single decoder instance with parallel sub-segments, the iterative process alternates between two distinct "softbit sets" (Systematic/Parity 1 and Interleaved Systematic/Parity 2). This alternating process allegedly corresponds to the operation of two logical, serially coupled soft decision decoders. (Compl. ¶¶18, 19). ¶18, ¶19 col. 4:9-11
providing at least one memory module coupled to an output of each of the first and second soft decision decoders, wherein the output of the memory module associated with the second soft decision decoder is fed back as an input of the first soft decision decoder; NI’s documentation allegedly describes a "QPP Reordering module" that handles interleaving and de-interleaving of extrinsic information between decoding half-iterations, and a "Stake Memory" that stores state probability vectors. These modules are alleged to perform the claimed memory and feedback functions. (Compl. ¶¶19, 23, 25). ¶19, ¶23, ¶25 col. 4:10-12, 4:21-26
processing systematic information data and extrinsic information data using the maximum a posteriori (AP) probability algorithm, and/or logarithm approximation algorithm; The accused products allegedly implement a Turbo Decoder based on the Max-Log-MAP algorithm, which is a type of MAP or logarithmic approximation algorithm, to process information as required by the LTE standard. (Compl. ¶¶15, 16). ¶15, ¶16 col. 2:40-45 (C1 Cert)
generating soft decision based on the maximum a posteriori (MAP) probability algorithm, and/or logarithm approximation algorithm; The complaint alleges that the use of the Max-Log-MAP algorithm in the accused products inherently generates soft decisions, such as Log-Likelihood Ratios (LLRs). (Compl. ¶¶17, 19). ¶17, ¶19 col. 2:46-49 (C1 Cert)
weighing and storing soft decision information into the corresponding memory module; The complaint alleges that standard-compliant Turbo decoding, as performed by the accused products, necessarily employs weighting of soft decisions (e.g., LLRs) and stores this information in memory modules (e.g., the alleged "QPP Reordering module" and "Softbit Input Buffer") for use in subsequent iterations. (Compl. ¶¶18, 19, 22). ¶18, ¶19, ¶22 col. 2:50-52 (C1 Cert)
performing, for a predetermined number of times, iterative decoding from the first to the last of multiple decoders, wherein an output from the last soft decision decoder is fed back as an input to the first soft decision decoder... and propagate to the last decoder in a circular circuit. NI’s documentation allegedly describes a decoding process of up to 4.5 full iterations (9 half-iterations). The complaint alleges this process involves feeding extrinsic information from one half-iteration back as input to the next, creating the claimed iterative feedback loop and circular circuit. (Compl. ¶¶20, 22, 32-33). ¶20, ¶22, ¶32, ¶33 col. 2:53-59 (C1 Cert)

Identified Points of Contention

  • Scope Questions: A central question may be whether the accused products, described in NI's documentation as having a single Turbo Decoder instance with four parallel sub-segment decoders (Compl. ¶18), can meet the claim limitation of "first and second soft decision decoders serially coupled." The complaint advances a theory of two logical decoders based on the sequential processing of different data sets, which raises the question of whether this functional sequence satisfies a structural or architectural claim limitation.
  • Technical Questions: What evidence does the complaint provide that the accused "Softbit Input Buffer" has the specific structure of "at least three shift registers" as recited in the claim? The infringement allegations focus heavily on the algorithmic and data-flow aspects of the method, with less detail on the specific hardware structures used to implement them.

V. Key Claim Terms for Construction

The Term: "first and second soft decision decoders serially coupled in a circular circuit"

  • Context and Importance: This term is at the core of the infringement dispute. The definition will determine whether an architecture that is physically parallelized but performs logically sequential operations can infringe. Practitioners may focus on this term because the complaint alleges infringement by a system described as having parallel decoder instances, creating an apparent mismatch with the "serially coupled" language. (Compl. ¶18).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's description of the invention focuses on the functional pipelined scheme and feedback loop. It states the decoder "utilizes two pipelined and serially concatenated SISO Log-MAP Decoders" and describes an iterative process where data is passed back and forth. (’742 Patent, col. 2:40-49). This functional language could support a construction that is not limited to two physically separate hardware blocks.
    • Evidence for a Narrower Interpretation: The patent's primary embodiment, shown in Figure 4, depicts two distinct boxes labeled "DECODER A" and "DECODER B." (’742 Patent, Fig. 4). This explicit structural depiction could be used to argue that the claim requires two physically or architecturally distinct decoders.

The Term: "input buffer comprising at least three shift registers"

  • Context and Importance: This is a structural limitation ("comprising...") within a method claim ("providing..."). Infringement of this element may depend on the actual hardware or simulated hardware structure of the accused buffer.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification's text describes the buffer's function: "Serial received data are shifted into 3 Shift Registers to produce R0, R1, and R2 data sequence." (’742 Patent, col. 4:36-39). A party could argue that any component that performs this function of creating three parallel data streams from a serial input meets the claim's requirement.
    • Evidence for a Narrower Interpretation: The claim language is specific, and Figure 5 explicitly illustrates three separate blocks, each labeled "N-BIT SHIFT REGISTER." (’742 Patent, Fig. 5). This could support a narrow construction requiring the specific structure shown, rather than just any functionally equivalent buffer.

VI. Other Allegations

The complaint does not contain sufficient detail for analysis of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of architectural interpretation: can the claim limitation "first and second soft decision decoders serially coupled" be construed to read on an allegedly infringing system that employs a single decoder instance with multiple parallel sub-segment decoders? The resolution may depend on whether the claim is interpreted to require two physically distinct hardware units, as depicted in the patent's figures, or if a logically sequential flow of information within a parallelized architecture is sufficient.
  • A key evidentiary question will be one of structural correspondence: does the accused "Softbit Input Buffer" possess the specific structure of "at least three shift registers" as required by the claim? While the complaint maps the functional flow of the decoding process in detail, the case may turn on whether discovery uncovers a direct structural mapping for hardware-oriented limitations like this one.