DCT

7:25-cv-00182

Redstone Logics LLC v. Advanced Micro Devices Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 7:25-cv-00182, W.D. Tex., 04/18/2025
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant has regular and established places of business within the Western District of Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s System-on-Chip (SoC) products, which implement the Zynq UltraScale+ Device architecture, infringe a patent related to power management and communication methods in multi-core processors.
  • Technical Context: The technology addresses power efficiency in multi-core processors by creating independent power and clock-speed domains for different groups of cores, enabling high-power operation only where needed.
  • Key Procedural History: The complaint does not reference any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

Date Event
2010-02-26 ’339 Patent Priority Date
2013-10-01 ’339 Patent Issue Date
2025-04-18 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor"

  • Patent Identification: U.S. Patent No. 8,549,339, "Processor core communication in multi-core processor," issued October 1, 2013.
  • The Invention Explained:
    • Problem Addressed: The patent's background notes that in conventional multi-core processors, all processor cores typically share the same supply voltage and clock signal, which limits opportunities for dynamic power management. (’339 Patent, col. 1:7-14).
    • The Patented Solution: The invention proposes partitioning a multi-core processor into distinct regions, or "stripes," where each stripe of processor cores can operate with an independent supply voltage and an independent clock signal. (’339 Patent, Abstract; col. 2:20-31). To manage communication between these separate domains, the patent describes an "interface block" that can use components like "level shifters" or "synchronizers" to reconcile the different voltage and clock signals, ensuring reliable data transfer between stripes. (’339 Patent, col. 3:25-34; col. 4:1-7).
    • Technical Importance: This architecture allows for more granular power management, enabling a processor to assign computationally intensive tasks to stripes running at high voltage and frequency, while assigning less demanding tasks to other stripes operating at lower power, thereby improving overall power efficiency. (’339 Patent, col. 2:41-60).
  • Key Claims at a Glance:
    • The complaint focuses on independent claim 1. (Compl. ¶11).
    • The essential elements of independent claim 1 are:
      • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first phase lock loop (PLL).
      • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL, where the first supply voltage and first clock signal are independent from the second.
      • An interface block coupled between the first and second sets of processor cores, configured to facilitate communication between them.
    • The complaint alleges infringement of "one or more claims," reserving the right to assert additional claims. (Compl. ¶8).

III. The Accused Instrumentality

  • Product Identification: The Accused Instrumentalities are identified as "products comprising one or more SoC each comprising two or more sets of processors implementing a Zynq UltraScale+ Device architecture (or similar architecture)." (Compl. ¶8).
  • Functionality and Market Context: The complaint does not provide specific details regarding the technical operation or features of the Zynq UltraScale+ architecture beyond identifying it by name. (Compl. ¶8). It also makes no specific allegations regarding the products' commercial importance or market position, other than alleging they are made, used, sold, and imported in the United States. (Compl. ¶4).

IV. Analysis of Infringement Allegations

The complaint alleges that a claim chart comparing independent claim 1 of the ’339 Patent to the Accused Instrumentalities is attached as Exhibit 2; however, this exhibit was not included with the filed complaint. (Compl. ¶11). The complaint’s narrative sections do not provide a detailed theory of infringement or map specific product features to the limitations of claim 1. No probative visual evidence provided in complaint.

  • Identified Points of Contention: Based on the claim language and the general nature of the accused technology, the infringement analysis may raise several key questions:
    • Scope Questions: A primary question will be whether the "Zynq UltraScale+ Device architecture" is organized into "sets of processor cores" that receive truly independent supply voltages and clock signals, as required by the claim. The case may turn on the degree of independence required to meet this limitation.
    • Technical Questions: A factual dispute may arise over whether the accused AMD SoCs contain a distinct "interface block" that performs the claimed function of facilitating communication between separate power and clock domains. The analysis will question what evidence shows that the accused architecture includes this specific claimed structure, rather than a more integrated bus or interconnect fabric that accomplishes a similar purpose through a different mechanism.

V. Key Claim Terms for Construction

  • The Term: "interface block"

    • Context and Importance: This term defines the core structural component that enables the invention's functionality. The existence of a structure corresponding to the "interface block" in the accused products is essential to the infringement case. Practitioners may focus on this term because its construction will determine whether a wide range of interconnect architectures can be read on by the claim, or if it is limited to more specific implementations.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim itself defines the term functionally as being "configured to facilitate communication between the first set of processor cores and the second set of processor cores." (’339 Patent, col. 8:2-5). This could support an interpretation covering any structure that performs this function.
      • Evidence for a Narrower Interpretation: The specification describes specific embodiments of the "interface block" as containing "level shifters" (Fig. 2) or "synchronizers" (Fig. 3). (’339 Patent, col. 3:25-34; col. 4:1-7). This could support a narrower construction requiring one of these specific components or a similar discrete hardware module.

  • The Term: "dynamically receive"

    • Context and Importance: This term is critical for defining the power management aspect of the invention. The infringement question will depend on whether the power delivery to the core sets in the accused products is "dynamic" in the manner contemplated by the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent’s background section introduces the concept in general terms as "dynamic supply voltage and clock speed control." (’339 Patent, col. 1:11-12). This could suggest the term encompasses any non-static power delivery scheme that adapts to changing conditions.
      • Evidence for a Narrower Interpretation: The detailed description links this function to a "power control block" that selects voltages based on "computational requirements" and maintains specific differential relationships between adjacent stripes. (’339 Patent, col. 2:41-65). An argument could be made that "dynamically receive" requires this type of sophisticated, task-aware control scheme.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement, stating that AMD provides "engineering documents," "user manuals and online instruction materials" that encourage and instruct customers to use the accused products in ways that infringe the ’339 Patent. (Compl. ¶9).
  • Willful Infringement: The complaint alleges that AMD has had knowledge of the ’339 Patent "at least the filing and service of this Complaint" and continues its allegedly infringing activities despite this knowledge. (Compl. ¶9). This allegation provides a basis for a claim of post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this dispute will likely depend on the court's interpretation of key claim terms and the underlying technical evidence. The central questions for the case appear to be:

  • A core issue will be one of structural correspondence: Does the accused Zynq UltraScale+ architecture contain a discrete "interface block" that maps onto the patent’s claimed structure, or is communication between processor domains handled through a different, more integrated architecture not contemplated by the patent?
  • A key evidentiary question will be one of functional operation: Do the processor core sets in the accused products "dynamically receive" supply voltages and clock signals that are truly independent from one another, and does the evidence show a level of dynamic control and independence sufficient to meet the specific limitations recited in the claims?