DCT
7:25-cv-00183
Redstone Logics LLC v. Apple Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Redstone Logics LLC (Texas)
- Defendant: Apple Inc. (California)
- Plaintiff’s Counsel: Russ August & Kabat
- Case Identification: 7:25-cv-00183, W.D. Tex., 04/18/2025
- Venue Allegations: Venue is alleged based on Defendant’s transaction of business and maintenance of regular and established places of business within the Western District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s Apple M-series System-on-Chip (SoC) products, which utilize performance and efficiency core architectures, infringe a patent related to managing communication between processor core sets operating on independent power and clock signals.
- Technical Context: The technology concerns power management in multi-core processors, a critical aspect of modern computing for balancing performance with energy efficiency in devices ranging from mobile phones to high-performance computers.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2010-02-26 | U.S. Patent No. 8,549,339 Priority Date (Application Filing) |
| 2013-10-01 | U.S. Patent No. 8,549,339 Issued |
| 2025-04-18 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,549,339 - Processor core communication in multi-core processor
- Patent Identification: U.S. Patent No. 8,549,339, Processor core communication in multi-core processor, issued October 1, 2013.
The Invention Explained
- Problem Addressed: In conventional multi-core processors, all processor cores typically share the same supply voltage and clock signal. While dynamic voltage and frequency scaling (DVFS) can reduce power consumption, this shared architecture limits the ability to finely tune power for different groups of cores performing different types of tasks, creating an efficiency problem. (’339 Patent, col. 1:5-14).
- The Patented Solution: The invention describes a multi-core processor divided into distinct regions or "stripes" (e.g., rows of cores), where each stripe can receive an independent supply voltage and an independent clock signal. (’339 Patent, col. 2:20-31). An "interface block" is positioned between these stripes to manage and synchronize communication, allowing, for example, a high-performance, high-power stripe of cores to communicate effectively with a low-power, efficiency-focused stripe of cores. (’339 Patent, Abstract; col. 4:1-17).
- Technical Importance: This architecture allows for more granular power management by assigning tasks with high computational requirements to high-power stripes and less demanding tasks to low-power stripes, optimizing overall processor efficiency. (’339 Patent, col. 2:41-60).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶11).
- Independent Claim 1: A multi-core processor comprising:
- a first set of processor cores... configured to dynamically receive a first supply voltage and a first output clock signal of a first phase lock loop (PLL) having a first clock signal as input;
- a second set of processor cores... configured to dynamically receive a second supply voltage and a second output clock signal of a second PLL having a second clock signal as input, wherein the first supply voltage is independent from the second supply voltage, and the first clock signal is independent from the second clock signal; and
- an interface block coupled to the first set of processor cores and also coupled to the second set of processor cores, wherein the interface block is configured to facilitate communication between the first set of processor cores and the second set of processor cores.
- The complaint does not explicitly reserve the right to assert dependent claims but alleges infringement of "one or more claims." (Compl. ¶8).
III. The Accused Instrumentality
Product Identification
- The Accused Instrumentalities are identified as products incorporating Apple's System-on-Chip (SoC) devices, specifically including the Apple M-series SoCs. (Compl. ¶8).
Functionality and Market Context
- The complaint alleges that the accused SoCs contain "two or more sets of processors implementing the Firestorm and Icestorm architecture (or similar architecture)." (Compl. ¶8). In public technical discourse, "Firestorm" cores are known as high-performance cores and "Icestorm" cores are known as high-efficiency cores. The complaint alleges these different sets of cores directly infringe the claims of the ’339 Patent. (Compl. ¶8).
- These SoCs are central to Apple's product lines, including Mac computers, iPads, and other devices, and are marketed based on their combination of high performance and power efficiency. The complaint does not provide further technical detail on the operation of the accused SoCs.
IV. Analysis of Infringement Allegations
The complaint references a claim chart in an unattached exhibit. (Compl. ¶11). The following chart summarizes the infringement theory based on the narrative allegations in the complaint. No probative visual evidence provided in complaint.
'339 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first set of processor cores of the multi-core processor, wherein each processor core from the first set of processor cores is configured to dynamically receive a first supply voltage and a first output clock signal... | The "Firestorm" (high-performance) cores within an accused Apple M-series SoC, which operate as a distinct set and receive their own supply voltage and clock signal. | ¶8 | col. 8:52-58 |
| a second set of processor cores of the multi-core processor, wherein each processor core from the second set... is configured to dynamically receive a second supply voltage and a second output clock signal... | The "Icestorm" (high-efficiency) cores within the same SoC, which operate as a second distinct set and receive their own supply voltage and clock signal. | ¶8 | col. 8:59-64 |
| ...wherein the first supply voltage is independent from the second supply voltage, and the first clock signal is independent from the second clock signal; and | The power and clock domains for the Firestorm cores are alleged to be independent of the power and clock domains for the Icestorm cores. | ¶8 | col. 8:62-9:2 |
| an interface block coupled to the first set of processor cores and also coupled to the second set of processor cores, wherein the interface block is configured to facilitate communication between the first... and the second set... | An interconnect fabric or similar circuitry within the Apple M-series SoC that manages communication and data transfer between the Firestorm and Icestorm core sets. | ¶8 | col. 8:1-5 |
- Identified Points of Contention:
- Technical Question: The complaint identifies the accused architecture by the marketing names "Firestorm" and "Icestorm." A central question will be what evidence demonstrates that these architectures, as implemented, meet the specific claim limitations, such as receiving independent clock signals from distinct PLLs and utilizing an "interface block" as described in the patent.
- Scope Questions: The infringement analysis may turn on whether Apple's implementation of a heterogeneous compute architecture falls within the scope of the patent's "sets of processor cores" arranged in "stripes." The patent primarily illustrates these as physical rows of cores, raising the question of whether the claims read on a more integrated SoC architecture where core sets are defined functionally rather than by physical arrangement. (’339 Patent, Fig. 1; col. 2:24-26).
V. Key Claim Terms for Construction
1. The Term: "a first set of processor cores" / "a second set of processor cores"
- Context and Importance: The definition of a "set" is fundamental to infringement. The complaint alleges that Apple's "Firestorm" and "Icestorm" cores constitute these "sets." (Compl. ¶8). The case may depend on whether this grouping aligns with the patent’s description of distinct "stripes" or "regions."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself does not require a specific number of cores per set or a particular physical layout, which may support an interpretation covering any logical grouping of cores operating on a common power/clock profile.
- Evidence for a Narrower Interpretation: The specification repeatedly describes the sets as "stripes" that correspond to physical "rows of the two-dimensional array." (’339 Patent, col. 2:22-26). This could support a narrower construction requiring a specific physical arrangement that may not be present in the accused SoCs.
2. The Term: "interface block"
- Context and Importance: This term is the structural element that enables the invention's core functionality. Plaintiff must prove the accused SoCs contain a structure that meets the definition of an "interface block."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim requires only that the block be "coupled to" the sets of cores and "configured to facilitate communication." This functional language could be argued to cover any interconnect or bus that performs this role. (’339 Patent, col. 8:1-5).
- Evidence for a Narrower Interpretation: The specification provides specific examples of an interface block containing "level shifters" to translate voltage levels (col. 3:27-50) or "synchronizers" to align different clock signals (col. 4:1-8). Defendant may argue that the term should be limited to structures containing these specific components, as depicted in Figures 2 and 3.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement, stating that Apple provides "engineering documents for customers that integrate the Accused Products into consumer devices" and "user manuals and online instruction materials" that encourage and instruct infringing use. (Compl. ¶9). It also alleges contributory infringement, stating the products are especially made or adapted for infringement and are not staple articles of commerce. (Compl. ¶10).
- Willful Infringement: Willfulness allegations appear to be based on knowledge of the patent acquired "through at least the filing and service of this Complaint," suggesting a theory of post-suit willfulness. (Compl. ¶9).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical mapping: Can Plaintiff produce evidence to show that the internal architecture of Apple's M-series SoCs, particularly the interconnect between its performance and efficiency cores, practices the specific "interface block" and independent PLL-driven clocking structures required by the asserted claim?
- The case will also involve a question of definitional scope: Does the term "set of processor cores," described in the patent's preferred embodiments as physical "stripes," read on the functionally distinct clusters of "Firestorm" and "Icestorm" cores in Apple's heterogeneous compute architecture?
- A key evidentiary question for indirect infringement will be specificity of intent: What specific instructions in Apple's "engineering documents" or "user manuals" actively instruct customers or end-users to operate the accused SoCs in a manner that directly infringes the method of managing communications as claimed?