Redstone Logics LLC v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Redstone Logics LLC (Texas)
  • Defendant: Nvidia Corporation (Delaware)
  • Plaintiff’s Counsel: Russ August & Kabat
• Case Identification: 7:25-cv-00184, W.D. Tex., 04/18/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant has transacted business, committed acts of infringement, and maintains a regular and established place of business in the District.
• Core Dispute: Plaintiff alleges that Defendant’s System-on-Chip (SoC) products implementing the Nvidia Jetson TX 2 architecture infringe a patent related to power management and communication in multi-core processors.
• Technical Context: The lawsuit concerns methods for dynamically adjusting power and clock speeds for different groups of cores within a single multi-core processor to improve power efficiency.
• Key Procedural History: The complaint does not mention any prior litigation, licensing history, or administrative proceedings involving the patent-in-suit.

Case Timeline

Date	Event
2010-02-26	U.S. Patent No. 8,549,339 Priority Date
2013-10-01	U.S. Patent No. 8,549,339 Issues
2025-04-18	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,549,339 - "Processor core communication in multi-core processor"

• Patent Identification: U.S. Patent No. 8,549,339, "Processor core communication in multi-core processor", issued October 1, 2013.

The Invention Explained

• Problem Addressed: The patent addresses the inefficiency of conventional multi-core processors where all processor cores generally share the same supply voltage and clock signal. This monolithic approach limits opportunities for granular power management, as the entire processor must operate at a power level sufficient for the most demanding task, even when other cores are less busy (’339 Patent, col. 1:7-14).
• The Patented Solution: The invention proposes dividing a multi-core processor into distinct regions, or "stripes," of processor cores (’339 Patent, col. 2:20-26). Each stripe can dynamically receive its own independent supply voltage and its own independent clock signal, allowing its power profile to be tailored to its specific computational load (’339 Patent, Abstract). To manage communication between these independently powered and clocked stripes, the invention uses an "interface block" that can include components like level shifters or synchronizers to translate signals between the different voltage and clock domains (’339 Patent, col. 8:1-13; Fig. 2-3).
• Technical Importance: This architecture enables more sophisticated dynamic voltage and frequency scaling (DVFS), allowing for significantly reduced power consumption in multi-core systems by not forcing low-activity cores to run at the same high power and frequency as high-activity cores (’339 Patent, col. 1:10-14, col. 3:17-21).

Key Claims at a Glance

• The complaint asserts independent claim 1 (Compl. ¶11).
• Claim 1 Essential Elements:
  • A first set of processor cores configured to dynamically receive a first supply voltage and a first output clock signal from a first phase lock loop (PLL).
  • A second set of processor cores configured to dynamically receive a second supply voltage and a second output clock signal from a second PLL, where the supply voltages and clock signals for the two sets are independent of each other.
  • An interface block coupled to both the first and second sets of processor cores, configured to facilitate communication between them.
• The complaint does not explicitly reserve the right to assert dependent claims, but alleges infringement of "one or more claims" of the patent (’339 Patent, col. 7:51-8:5; Compl. ¶8).

III. The Accused Instrumentality

Product Identification

• The complaint identifies the "Accused Instrumentalities" as products comprising one or more System-on-Chips (SoCs) that implement the "Nvidia Jetson TX 2 architecture (or similar architecture)" (Compl. ¶8).

Functionality and Market Context

• The complaint alleges that the accused SoCs contain "two or more sets of processors" (Compl. ¶8). It does not provide further technical detail regarding the specific operation of the Jetson TX 2 architecture, its power domains, clocking mechanisms, or inter-core communication fabric. The complaint does not contain allegations regarding the product's specific commercial importance or market position.

IV. Analysis of Infringement Allegations

The complaint states that a claim chart comparing independent claim 1 to the accused products is attached as Exhibit 2, but this exhibit was not included with the filed complaint (Compl. ¶11). The narrative infringement theory alleges that the Accused Instrumentalities, which are described as having "two or more sets of processors," satisfy all limitations of claim 1 (Compl. ¶8, ¶11). The core of the allegation is that the architectural division of processors in the Nvidia Jetson TX 2 platform maps onto the claimed "first set" and "second set" of processor cores, and that these sets operate with the independent power and clocking schemes recited in the patent. No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Scope Questions: A central question will be whether the grouping of processors in the accused Nvidia architecture constitutes a "first set" and "second set" as contemplated by the patent. The patent describes these sets as "stripes" or rows in an array, which raises the question of whether other architectural groupings (e.g., a high-performance cluster and a high-efficiency cluster) fall within the claim's scope (’339 Patent, col. 2:23-26).
  • Technical Questions: The infringement analysis will depend on evidence showing that the accused SoCs actually implement (1) supply voltages and clock signals for different processor sets that are truly "independent" as claimed, and (2) a distinct "interface block" that performs the functions of facilitating communication between these separately-clocked and separately-powered domains, as opposed to a more generalized bus architecture.

V. Key Claim Terms for Construction

The Term: "interface block"

• Context and Importance: This term is the structural and functional nexus between the independently-powered "sets" of cores. Its construction will be critical to determining infringement. If construed narrowly to require specific hardware disclosed in the embodiments, infringement may be more difficult to prove. If construed broadly, it may cover a wider range of inter-core communication hardware.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claim language itself is functional, stating the block is "configured to facilitate communication" ('339 Patent, col. 8:3-5). This suggests a focus on the block's purpose rather than its specific structure.
  • Evidence for a Narrower Interpretation: The specification's embodiments depict the "interface block" as containing specific components like a "level shifter" or a "synchronizer" to handle mismatched voltage and clock domains (’339 Patent, Fig. 2-3, col. 8:6-13). A defendant may argue these embodiments limit the term to structures containing such specific circuits.

The Term: "a first set of processor cores" / "a second set of processor cores"

• Context and Importance: The definition of a "set" will determine whether the accused product's architecture meets this fundamental limitation. The complaint alleges the accused SoCs have "two or more sets of processors," directly implicating this term (Compl. ¶8).
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term "set" is general. Plaintiff may argue it should be given its plain and ordinary meaning, covering any logical or physical grouping of processor cores.
  • Evidence for a Narrower Interpretation: The specification repeatedly refers to the processor cores being arranged in "rows" and these rows being referred to as a "stripe," which corresponds to a "region" (’339 Patent, col. 2:20-26). A defendant may argue that a "set" is limited to a physical row of cores in a 2-dimensional array, as depicted in Figure 1.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement under 35 U.S.C. § 271(b), asserting that Nvidia provides "engineering documents," "user manuals," and "online instruction materials" that actively encourage and instruct customers and end users to use the accused products in an infringing manner (Compl. ¶9). The complaint also alleges contributory infringement under 35 U.S.C. § 271(c), stating the products are especially made or adapted for infringement and are not staple articles of commerce (Compl. ¶10).
• Willful Infringement: The complaint does not allege pre-suit knowledge. It asserts that Nvidia has had knowledge of the ’339 Patent and its infringement "Through at least the filing and service of this Complaint," creating a basis for potential post-filing willfulness (Compl. ¶9).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: can the term "set of processor cores", which the patent illustrates as physical "stripes" or rows in an array, be construed to cover the potentially different logical and physical processor groupings (e.g., performance clusters vs. efficiency clusters) used in the accused Nvidia Jetson TX 2 architecture?
2. A second central issue will be structural and functional equivalence: does the inter-core communication hardware in the accused SoCs constitute an "interface block" as claimed? This will require the court to determine whether the term is limited to the specific "level shifter" and "synchronizer" embodiments in the patent or can encompass a more generic communication fabric that facilitates communication between independently powered and clocked core groups.
3. An ultimate evidentiary question will be one of technical proof: what evidence will demonstrate that the accused architecture implements not just different power modes, but truly "independent" supply voltages and clock signals for different sets of cores, and that a specific, identifiable "interface block" manages the communication between them as required by the claims.