TurboCode LLC v. Renesas Electronics America Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: TurboCode LLC (Texas)
  • Defendant: Renesas Electronics America Inc. (California)
  • Plaintiff’s Counsel: Direction IP Law
• Case Identification: 7:25-cv-00459, W.D. Tex., 10/08/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant maintains a regular and established place of business in Austin, Texas.
• Core Dispute: Plaintiff alleges that Defendant’s cellular Internet of Things (IoT) modules, which comply with the 4G/LTE-M standard, infringe a patent related to high-speed, power-efficient turbo code decoder architectures.
• Technical Context: The technology concerns turbo codes, a class of forward error-correction codes used in digital communications standards like 3G and 4G/LTE to achieve reliable data transmission close to theoretical limits, particularly in noisy wireless environments.
• Key Procedural History: The patent-in-suit, U.S. Patent No. 6,813,742, was the subject of an ex parte reexamination, which concluded with the issuance of a Reexamination Certificate on February 10, 2009. The asserted claim, claim 6, is a reexamined claim from that certificate, suggesting its validity was reviewed and confirmed by the USPTO over prior art after its initial issuance.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,813,742 - “High Speed Turbo Codes Decoder for 3G Using Pipelined SISO Log-Map Decoders Architecture”

The Invention Explained

• Problem Addressed: The patent’s background section states that decoding turbo codes, while effective, was computationally complex and difficult to implement efficiently in the hardware of consumer wireless devices. Prior art methods were described as costly, power-intensive, and too slow for the high data rates of emerging 3G applications (’742 Patent, col. 2:12-22).
• The Patented Solution: The invention discloses a decoder architecture using two pipelined Soft-In/Soft-Out (SISO) Log-MAP decoders connected in a feedback loop via interleaver and de-interleaver memories (’742 Patent, col. 2:40-51; Fig. 4). This pipelined structure allows the two decoders to work in parallel on different stages of the iterative decoding process, which is intended to increase data throughput significantly, producing a decoded output on each clock cycle, while using simpler hardware (e.g., binary adders instead of multipliers) to reduce complexity and power consumption (’742 Patent, col. 2:52-60).
• Technical Importance: The described architecture aimed to make high-performance turbo decoding practical for mass-market mobile devices by improving speed and power efficiency over prior art implementations (’742 Patent, col. 2:32-40).

Key Claims at a Glance

• The complaint asserts independent claim 6 of the Ex Parte Reexamination Certificate (Compl. ¶12).
• The essential elements of claim 6 are:
  • A method of iteratively decoding received baseband signals.
  • Providing an input buffer with at least three shift registers to receive an input signal and generate first, second, and third shifted input signals.
  • Providing first and second soft decision decoders serially coupled in a circular circuit, where each decoder processes soft decision output from the preceding decoder, and where the decoders also receive the shifted input signals from the input buffer.
  • Providing at least one memory module coupled to the output of each decoder, where the output of the memory associated with the second decoder is fed back as an input to the first decoder.
  • Processing systematic and extrinsic information data using a maximum a posteriori (MAP) probability algorithm or a logarithm approximation thereof.
  • Generating a soft decision based on the MAP algorithm or its logarithm approximation.
  • Weighing and storing the soft decision information into the corresponding memory module.
  • Performing iterative decoding for a predetermined number of times, with output from the last decoder fed back as input to the first decoder in a circular circuit.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The Renesas RYZ014A LTE Cat-M1 Cellular IoT Module and other similar products that comply with 4G/LTE and LTE-Machine Type (“LTE-M”) communication standards as defined by 3GPP Releases 13 and 14 (Compl. ¶¶12, 14). The complaint notes the RYZ014A module incorporates a Monarch SQN3330 baseband chip (Compl. p. 6).

Functionality and Market Context

The accused products are modules that provide cellular connectivity for IoT devices (Compl. p. 5). A core function of these modules is performing channel coding and decoding to ensure reliable communication over a wireless channel, as required by the LTE standard (Compl. p. 7). The complaint alleges that the LTE standard, and therefore the accused products, mandates the use of turbo coding for certain data channels (Compl. p. 7). It further alleges that this implementation involves iterative decoding using probabilistic "soft information" to refine decoding accuracy over multiple passes (Compl. p. 8). A diagram from a technical article included in the complaint shows a turbo decoder architecture with two sub-decoders coupled in a circular loop, which Plaintiff alleges describes the operation of the Accused Instrumentalities (Compl. p. 25, Fig. 3). The complaint asserts that LTE-M operates within the existing LTE network infrastructure and uses consistent protocols, including for turbo decoding (Compl. ¶15).

IV. Analysis of Infringement Allegations

’742 Patent Infringement Allegations

Identified Points of Contention:

• Scope Questions: A central question may be whether the accused product's architecture, which is designed to comply with the LTE standard, meets the specific structural limitations of the claims. For instance, does an LTE turbo decoder, which may be implemented as a single, time-multiplexed hardware unit, constitute "first and second soft decision decoders serially coupled" as distinct structures required by the claim?
• Technical Questions: The complaint alleges the presence of "at least three shift registers" by inference, stating that the LTE-M standard's functionality "corresponds to providing shifted versions of the input sequence" even though the standard "does not explicitly disclose shift registers" (Compl. ¶15). This raises the question of whether the accused product's input buffering mechanism is structurally a set of "shift registers" or a functionally equivalent alternative, such as a pointer-based RAM buffer, and whether the latter falls within the scope of the claim term.

V. Key Claim Terms for Construction

• The Term: "soft decision decoders serially coupled in a circular circuit"

  • Context and Importance: This term defines the core architecture of the invention. The dispute will likely hinge on whether the accused devices, which execute an iterative decoding algorithm, embody the claimed structure of two distinct decoders coupled in a specific way, or if they use a single, re-used hardware block that functionally simulates this process.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes the decoders' operation in a functional, pipelined manner: "while the first decoder is decoding data in the de-interleaver-Memory, the second decoder performs decoding data in the interleaver-Memory" (’742 Patent, col. 2:45-48). This functional description could support an interpretation where any implementation that performs these two distinct decoding steps iteratively infringes.
    • Evidence for a Narrower Interpretation: The patent’s primary block diagram, Figure 4, depicts two physically separate blocks labeled "DECODER A" (42) and "DECODER B" (44). This could support a narrower construction requiring two distinct hardware decoders, not just two algorithmic steps performed by one hardware unit.

• The Term: "input buffer comprising at least three shift registers"

  • Context and Importance: Infringement of this element appears to rely on an inference that the accused product's buffering function is structurally equivalent to "shift registers." The definition of this term will be critical.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's purpose is to receive and process input data streams R0, R1, and R2 (’742 Patent, col. 4:11-13). An argument could be made that any buffer circuit that reliably produces these three parallel, time-shifted streams for the decoders meets the claim's objective, regardless of its specific implementation.
    • Evidence for a Narrower Interpretation: Figure 5 of the patent explicitly shows three blocks, each labeled "N-BIT SHIFT REGISTER" (’742 Patent, Fig. 5). This explicit depiction of a specific hardware component may support a narrow construction that excludes other types of memory buffers, such as a general-purpose RAM that uses address pointers to create delays.

VI. Other Allegations

• Indirect Infringement: The complaint pleads a single count for direct infringement and does not include separate counts or detailed factual allegations for induced or contributory infringement (Compl. ¶12).
• Willful Infringement: The complaint does not contain an explicit allegation of willful infringement. It alleges constructive notice of the patent "by operation of law," which does not, on its own, typically support a claim for willfulness (Compl. ¶23).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case will likely depend on the court's construction of key structural claim terms and the evidence mapping the accused LTE-M standard-compliant products onto that construction.

• A core issue will be one of structural interpretation: does the accused product's turbo decoder, likely implemented as a single, efficient hardware block that executes an iterative algorithm, satisfy the claim requirement for "first and second soft decision decoders serially coupled," or does the claim demand two physically distinct decoder circuits as depicted in the patent’s figures?
• A key evidentiary question will be one of structural equivalence: can the complaint's inference that providing three time-delayed data streams is equivalent to the claimed "input buffer comprising at least three shift registers" overcome a potential defense that "shift register" is a specific hardware structure not present in the accused devices?