PTAB

IPR2013-00064

ChiMei Innolux Corp v. Semiconductor Energy Laboratory Co Ltd

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1. Case Identification

2. Patent Overview

  • Title: Electro-Optical Device and Thin Film Transistor and Method for Forming the Same
  • Brief Description: The ’311 patent describes a method for fabricating a thin-film transistor (TFT) used in display devices. The purported invention involves a specific manufacturing sequence and results in a "step-like" structure where an upper portion of the source and drain regions extends beyond a lower portion of their respective electrodes, allegedly shortening the distance between the regions.

3. Grounds for Unpatentability

Ground 1: Obviousness over Taniguchi, Mori, Kato, and Van Zant - Claims 9-11, 15, 17-19, 48, 51, and 52 are obvious over Taniguchi in view of Mori, Kato, and Van Zant.

  • Prior Art Relied Upon: Taniguchi (Japanese Patent Publication No. H2-234125), Mori (Patent 5,270,567), Kato (Patent 5,054,887), and Van Zant (Microchip Fabrication, 2nd ed. 1990).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Taniguchi taught a nearly identical method for manufacturing a TFT, disclosing all major process steps recited in independent claim 9. To the extent Taniguchi did not explicitly disclose the claimed "step-like" structure where the source/drain regions extend beyond the electrodes, Mori taught this exact feature. Mori disclosed that creating such a structure via overetching reduces parasitic capacitance between the gate and the source/drain, a known problem in TFT design. Kato was cited for its disclosure of forming a pixel electrode over a passivation film, and Van Zant was cited for its general teaching of wet etching processes common in semiconductor fabrication.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSA) would combine Taniguchi’s TFT fabrication method with Mori’s step-like electrode structure to solve the well-known problem of parasitic capacitance that Mori explicitly addressed. The combination involved applying a known technique (Mori's structure) to a similar device (Taniguchi's TFT) to obtain predictable results.
    • Expectation of Success: A POSA would have a reasonable expectation of success because combining the known manufacturing steps of Taniguchi with the known capacitance-reducing structure from Mori was a straightforward application of established semiconductor processing techniques.

Ground 2: Obviousness over Noguchi, Mori, Koden, Kato, and Van Zant - Claims 9-11, 15, 17-19, 48, 51, and 52 are obvious over Noguchi in view of Mori, Koden, Kato, and Van Zant.

  • Prior Art Relied Upon: Noguchi (Japanese Patent Publication No. H1-144682), Mori (Patent 5,270,567), Koden (Patent 4,862,234), Kato (Patent 5,054,887), and Van Zant (Microchip Fabrication, 2nd ed. 1990).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 1, asserting that Noguchi, like Taniguchi, taught a substantially similar TFT manufacturing process. Petitioner contended that Noguchi disclosed the fundamental steps of forming the gate, insulating layers, semiconductor layers, and electrodes. As with the previous ground, Petitioner argued that Mori supplied the critical teaching of the "step-like" structure created by overetching to reduce the distance between source/drain regions. Koden was cited for teachings on patterning semiconductor films, while Kato and Van Zant served the same purpose as in Ground 1.
    • Motivation to Combine: The motivation was identical to Ground 1: a POSA would be motivated to incorporate Mori's solution for reducing parasitic capacitance into the TFT design disclosed by Noguchi to improve device performance in a predictable manner.
    • Expectation of Success: The expectation of success was high, as it involved the integration of known structural features and processing steps for their intended and well-understood purposes.

Ground 3: Obviousness over Matsuzaki, Mori, Kwasnick, Kato, and Van Zant - Claims 9-11, 15, 17-19, 48, 51, and 52 are obvious over Matsuzaki in view of Mori, Kwasnick, Kato, and Van Zant.

  • Prior Art Relied Upon: Matsuzaki (Japanese Patent Publication No. H1-180523), Mori (Patent 5,270,567), Kwasnick (Patent 5,198,694), Kato (Patent 5,054,887), and Van Zant (Microchip Fabrication, 2nd ed. 1990).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Matsuzaki, like the primary references in the other grounds, disclosed a TFT structure and manufacturing method that anticipated most of the challenged claims. In fact, Petitioner asserted Matsuzaki explicitly described creating a step-like structure to prevent undercutting of the source and drain regions. Mori was cited as an alternative or cumulative reference for this structure and its benefits. Kwasnick was cited for its teachings on forming a passivation layer over the TFT structure.
    • Motivation to Combine: A POSA would combine Matsuzaki's process with the teachings of Mori and Kwasnick to create a robust TFT with both reduced parasitic capacitance (from Mori/Matsuzaki) and a protective passivation layer (from Kwasnick). This combination represented an optimization of known design choices.
    • Expectation of Success: A POSA would expect success in combining these elements, as each addressed a distinct and well-understood aspect of TFT fabrication and performance.

4. Key Claim Construction Positions

  • "overetching": Petitioner argued this term required no special construction beyond its plain and ordinary meaning as understood by a POSA. It asserted that "overetching" was a well-known semiconductor process. To support this, Petitioner pointed to a claim construction order and summary judgment ruling from a district court case involving the related ’258 patent, where the court and the Patent Owner (Semiconductor Energy Laboratory) agreed that overetching was a well-known process. This construction was central to the obviousness arguments, as Petitioner contended that references like Mori explicitly taught using this standard process to achieve the claimed step-like structure.

5. Key Technical Contentions (Beyond Claim Construction)

  • Administrative Estoppel: A central contention throughout the petition was that the claims of the ’311 patent were patentably indistinct from the claims of a related, earlier-issued ’258 patent. The ’258 patent had been subject to an inter partes reexamination where numerous claims were cancelled or disclaimed as unpatentable. Petitioner provided a detailed comparison chart arguing that the ’311 patent claims were merely obvious variants of the surrendered subject matter. Therefore, Petitioner argued that administrative estoppel should prevent the Patent Owner from re-litigating the patentability of subject matter it had already effectively conceded was unpatentable.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 9-11, 15, 17-19, 48, 51, and 52 of the ’311 patent as unpatentable under 35 U.S.C. §103.