PTAB

IPR2013-00064

Chimei Innolux Corp v. Semiconductor Energy Laboratory Co Ltd

Title: Electro-Optical Device and Thin Film Transistor and Method for Forming the Same
Brief Description: The ’311 patent describes a method for fabricating a thin-film transistor (TFT) where a key feature is a "step-like" structure. This structure is characterized by an upper portion of the source and drain regions extending beyond a lower portion of the source and drain electrodes, allegedly shortening the distance between the regions.

Prior Art Relied Upon: Taniguchi (Japanese Patent Publication No. JP H2-234125) and Mori (Patent 5,270,567).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Taniguchi taught a method of manufacturing a TFT that disclosed nearly all the process steps recited in the independent claims, including forming gate, insulating, semiconductor, and conductive layers. However, Taniguchi did not explicitly disclose the claimed "step-like" structure where the source/drain regions extend beyond the electrodes. Petitioner asserted that Mori explicitly disclosed this exact step-like structure, teaching that it reduces or eliminates parasitic capacitance between the gate and the source/drain electrodes.
- Motivation to Combine: A POSITA would combine Mori’s step-like structure with Taniguchi’s TFT manufacturing method to gain the known benefit of reduced gate-to-source and gate-to-drain capacitance, which was a well-known problem in the art.
- Expectation of Success: A POSITA would have a high expectation of success because incorporating the specific etching step from Mori to create the step-like structure was a predictable modification of the standard TFT fabrication process taught by Taniguchi.

Prior Art Relied Upon: Noguchi (Japanese Patent Publication No. JP H1-144682), Mori (Patent 5,270,567), and Koden (Patent 4,862,234).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Noguchi, like Taniguchi, taught a TFT manufacturing method nearly identical to that claimed in the ’311 patent but without the specific step-like structure. Koden was cited for its disclosure of patterning semiconductor films using a photomask, a step Petitioner argued was missing from Noguchi but would have been an obvious process choice. The key step-like structure limitation was again supplied by Mori, which taught the structure and its benefits.
- Motivation to Combine: A POSITA would combine Noguchi's TFT fabrication process with Mori's step-like structure for the same reason as in Ground 1: to reduce parasitic capacitance. Koden would be consulted to implement a conventional and well-understood patterning technique if it were deemed necessary to supplement Noguchi's teachings.
- Expectation of Success: The combination was argued to be a predictable substitution of one known TFT fabrication process (Noguchi) for another (Taniguchi) and the predictable incorporation of a known beneficial feature (Mori's step-like structure).

Prior Art Relied Upon: Taniguchi (Japanese Patent Publication No. JP H2-234125), Mori (Patent 5,270,567), and Kato (Patent 5,054,887).
Core Argument for this Ground:
- Prior Art Mapping: This ground built upon the combination of Taniguchi and Mori from Ground 1. It addressed additional limitations in claims 17-19 and 52, specifically the step of forming a pixel electrode over the passivation film and connecting it to the source or drain electrode. Petitioner asserted that Kato taught this exact configuration, disclosing a protective insulating layer (passivation film) over a TFT and a picture element electrode formed on top of it, connected to the drain electrode.
- Motivation to Combine: A POSITA building a display device using the Taniguchi/Mori TFT would naturally look to a reference like Kato to implement the standard, necessary structure of a pixel electrode for an active-matrix display.
- Expectation of Success: Integrating a pixel electrode as taught by Kato onto the TFT structure of Taniguchi/Mori was argued to be a routine and predictable step in the overall design of a complete display device.
Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations involving Matsuzaki (Japanese Patent Publication No. H1-180523) as the primary reference, in view of Mori, Kwasnick, Kato, and Van Zant, which relied on similar arguments for combination.

Petitioner argued that the term “overetching” should be given its plain and ordinary meaning, referring to a semiconductor process that was well-known long before the ’311 patent’s filing date. Petitioner noted that the same term was construed in litigation involving a related patent (’258 patent) and that the Patent Owner had agreed that the term was bound by this earlier construction, which confirmed it was a well-known part of every etching process.

Petitioner argued that administrative estoppel should prevent the Patent Owner from asserting the validity of the challenged claims. This argument was based on the prosecution history of a sibling patent, the ’258 patent, which was subject to an inter partes reexamination. In that proceeding, claims nearly identical to those in the ’311 patent were cancelled or disclaimed. Petitioner contended that the challenged claims of the ’311 patent were patentably indistinct from the surrendered subject matter of the ’258 patent, and therefore the Patent Owner was estopped from re-litigating their patentability.

Petitioner requested the institution of an inter partes review and the cancellation of claims 9-11, 15, 17-19, 48, 51, and 52 of the ’311 patent as unpatentable.