InvenSense Inc v. STMicroelectronics Inc

1. Case Identification

• Case #: IPR2013-00254
• Patent #: 6,034,419
• Filed: April 24, 2013
• Petitioner(s): InvenSense, Inc.
• Challenged Claims: 1-13

2. Patent Overview

• Title: Semiconductor Device With A Tungsten Contact
• Brief Description: The ’419 patent describes a semiconductor device, such as a CMOS transistor, that incorporates tungsten contacts. The purported invention addresses problems in prior art devices by introducing a "sealing dielectric layer" (e.g., silicon nitride) positioned between a bottom oxide layer and an upper interlevel dielectric layer to prevent defects like tungsten encroachment during fabrication.

3. Grounds for Unpatentability

Ground 1: Claims 1-5 and 8-13 are anticipated by Humphreys, and Claim 6 is obvious over Humphreys.

• Prior Art Relied Upon: Humphreys (Patent 3,961,414).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Humphreys discloses every element of the challenged claims. It teaches a semiconductor structure with doped regions on a silicon substrate, tungsten contacts, and a series of dielectric layers. Specifically, Humphreys discloses a silicon oxide layer (coating 12) on the substrate, a contiguous silicon nitride layer (coating 14) acting as the claimed "sealing layer," and a blanket glass layer (layer 26) acting as the claimed "interlevel layer." The interconnect layer taught by Humphreys is non-overlapping on at least one side of the contact, meeting that limitation as well.
  • Motivation to Combine (for §103 grounds): For claim 6 (requiring a field effect transistor), Petitioner argued it would have been obvious to a person of ordinary skill in the art (POSITA) to implement the structure taught by Humphreys in a CMOS field effect transistor, as this was a common application for such semiconductor structures.
  • Key Aspects: Petitioner asserted that functional limitations, such as the sealing layer's ability to modify stress or limit tungsten encroachment (claims 3, 8, 9, 13), are inherent properties of the silicon nitride layer disclosed by Humphreys.

Ground 2: Claims 1-13 are obvious over the Admitted Prior Art in view of Humphreys, Smith, or Manley.

• Prior Art Relied Upon: Admitted Prior Art ("APA") from the ’419 patent, Humphreys (Patent 3,961,414), Smith (Patent 5,055,423), and Manley (Patent 5,084,414).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that the ’419 patent’s own Figure 1, labeled "PRIOR ART," discloses a conventional CMOS device that meets nearly every limitation of claim 1, including the silicon substrate, doped regions, tungsten contacts, contact holes, a bottom oxide layer, an interlevel dielectric layer, and an interconnect. The primary element not explicitly shown in the APA is the "sealing layer" between the oxide and interlevel layers. Each of Humphreys, Smith, and Manley explicitly discloses adding such a sealing layer (typically silicon nitride) in a similar dielectric stack.
  • Motivation to Combine (for §103 grounds): A POSITA, starting with the conventional device shown in the APA, would have been motivated to incorporate the sealing layer taught by Humphreys, Smith, or Manley. The ’419 patent itself identifies problems like tungsten encroachment that the sealing layer is intended to solve. Since these references taught using a silicon nitride sealing layer for its known benefits of preventing diffusion and protecting underlying layers, it would have been an obvious modification to add this known element to the conventional APA device to achieve a predictable improvement in device reliability and performance.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success, as this combination merely involved applying a known material layer (silicon nitride) within a standard semiconductor structure to achieve its well-understood barrier properties.

Ground 3: Claims 1-11 and 13 are obvious over Iyer in view of Moslehi.

• Prior Art Relied Upon: Iyer (Patent 4,617,087) and Moslehi (Patent 4,888,087).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Iyer discloses a foundational integrated circuit with a silicon substrate, doped regions, and tungsten contacts disposed in contact holes. However, Iyer's dielectric structure is simple. Moslehi, which relates to the same field of forming tungsten contacts, teaches a more sophisticated multi-layer dielectric structure. Moslehi’s structure includes a bottom oxide layer, a silicon nitride layer deposited on the oxide layer (the "sealing layer"), and a second, thicker oxide layer deposited on the nitride layer (the "interlevel layer").
  • Motivation to Combine (for §103 grounds): A POSITA would combine Iyer and Moslehi because both references address the fabrication of tungsten contacts in integrated circuits. To improve the device in Iyer, a POSITA would have looked to contemporaneous art like Moslehi for improved dielectric layering schemes. Incorporating Moslehi's advanced dielectric stack—which includes the claimed sealing layer—into Iyer's device was argued to be a predictable combination of known semiconductor processing techniques to enhance device integrity and performance.
  • Expectation of Success (for §103 grounds): Success would be expected as the combination involves integrating well-known dielectric layers taught by Moslehi into a standard semiconductor device structure as shown in Iyer.

• Additional Grounds: Petitioner asserted additional challenges, including anticipation by Smith and Manley, and obviousness combinations involving Moriya (a 1983 technical paper), Shirai (Patent 4,271,582), Deleonibus (Patent 4,592,802), and Iyer alone. These grounds relied on similar arguments that the references, singly or combined, taught all claimed structural elements, with functional properties being inherent to the disclosed materials.

4. Key Claim Construction Positions

• "sealing layer": Petitioner proposed this term be construed as "a layer of silicon nitride or other substance that provides resistance to diffusion of fluorides along an oxide/silicon interface." This construction was critical for identifying the layer in prior art that taught silicon nitride for its barrier properties, even if not explicitly for "sealing."
• "interlevel layer": Petitioner proposed this term be construed as "a layer of dielectric material, for example, borophosphosilicate glass (BPSG), disposed on the sealing layer." This construction helped delineate the claimed three-layer dielectric stack (oxide, sealing, interlevel) within the prior art references.

5. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-13 of the ’419 patent as unpatentable.