PTAB

IPR2013-00384

Samsung Electronics Co Ltd v. US Ethernet Innovations LLC

Key Events

Petition

petition Intelligence

Title: Managing Peripheral Interrupts in a Computer System
Brief Description: The ’874 patent relates to an apparatus for managing peripheral interrupts using a two-level masking structure. The claimed invention purports to overcome the limitations of prior art single-level masking systems by creating a hierarchy of status information, allowing a host CPU to receive notice of a second event that occurs during an interrupt service routine for a first event without generating an additional interrupt.

Prior Art Relied Upon: IBM PC Ethernet Controller (a March 1983 technical specification), which explicitly describes the combination of an Intel 8259A Programmable Interrupt Controller (PIC) and a SEEQ 8001 Network Interface Controller (NIC).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that the IBM reference discloses every element of the challenged claims. The SEEQ 8001 NIC provides the claimed "first mask logic" via its transmit and receive control registers, which can mask interrupt signals from network events. The Intel 8259A PIC provides the "second mask logic" via its Mask Latch and associated AND gate. The required memory locations are also present, with the PIC's Request Latch serving as the "first memory location" and its In Service Latch serving as the "second memory location," creating the complete two-level masking architecture.
- Key Aspects: This ground asserted that a standard, commercially documented system configuration from the early 1980s contained the exact two-level interrupt masking structure that the ’874 patent claimed as its novel invention over a decade later.

Prior Art Relied Upon: Intel 8259A (a 1988 datasheet) and SEEQ 8001 NIC (a 1982 datasheet).
Core Argument for this Ground:
- Prior Art Mapping: As an alternative to Ground 1, Petitioner argued that even if not explicitly combined in a single reference, the combination of the Intel 8259A PIC and the SEEQ 8001 NIC was obvious. The Intel 8259A was a ubiquitous interrupt controller, and the SEEQ 8001 was a known network controller. The SEEQ 8001 NIC provides a first level of masking for network events, and the Intel 8259A provides a second, more general level of interrupt masking, thereby teaching all elements of the claimed two-level structure.
- Motivation to Combine: A POSITA would combine these components for several reasons: it was a known and predictable method of adding network functionality to a computer system, it represented a simple substitution of one type of peripheral (a NIC) for any other peripheral commonly connected to a PIC, and it was an obvious design choice from a finite number of known NICs and PICs available at the time.
- Expectation of Success: A POSITA would have had a high expectation of success, as connecting peripherals to a programmable interrupt controller like the Intel 8259A was a routine and well-understood task in computer architecture.

Prior Art Relied Upon: Intel 8259A (a 1988 datasheet).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that a standard, documented configuration of the Intel 8259A chip itself anticipates the claimed two-level masking structure, without needing to be combined with a separate peripheral. In "cascade mode," multiple 8259A PICs are chained together. A "slave" PIC provides the "first mask logic" and "first memory" for a set of interrupts. Its output is fed to a "master" PIC, which provides the "second mask logic" and "second memory," creating the claimed hierarchical structure. All required masking logic and memory latches are inherent to this standard operating mode.
Additional Grounds: Petitioner asserted numerous additional anticipation and obviousness challenges based on different prior art combinations. These included grounds based on the NSC PICs datasheet (asserted to anticipate when used in cascade mode), and obviousness combinations of NSC PICs with the SEEQ 8001 NIC or the DP8390 NIC. Further obviousness grounds were asserted based on combinations of the Shizuo patent with the Intel 8259A, SEEQ 8001 NIC, or DP8390 NIC.

"interrupt means" (Claim 1): The petition addressed the construction of this means-plus-function term, which was disputed in parallel district court litigation. Petitioner adopted the district court's tentative construction for the purposes of the IPR petition:
- Function: generating the interrupt signal to the host.
- Structure: Interrupt Controller 60 as depicted in Figure 4 and described in column 7, lines 55-63 of the ’874 patent, and structural equivalents thereto.
This construction was central because Petitioner argued that the prior art interrupt controllers (e.g., Intel 8259A, NSC PICs) were either identical to the disclosed structure or were well-known structural equivalents that performed the identical function in the same way to achieve the same result.

Patent Owner’s Infringement Theory Maps to Prior Art: A central contention was that the Patent Owner’s own infringement theory in district court litigation—accusing systems that combine a peripheral (with a first mask) and a separate interrupt controller (with a second mask)—describes a configuration that was routine practice and explicitly disclosed in the prior art. Petitioner argued that the IBM PC Ethernet Controller reference, for example, is a direct embodiment of this very architecture. This contention framed the invalidity argument by asserting that the scope of infringement sought by the Patent Owner squarely covers well-known prior art systems.

Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 6-9, 21-27, 29, and 30 of Patent 5,530,874 as unpatentable.