Mentor Graphics Corp v. Synopsys Inc

1. Case Identification

• Case #: IPR2014-00287
• Patent #: 6,836,420
• Filed: December 21, 2013
• Petitioner(s): Mentor Graphics Corporation
• Patent Owner(s): Synopsys, Inc.
• Challenged Claims: 1-3, 10-13, and 20

2. Patent Overview

• Title: Method And Apparatus For Resetable Memory And Design Approach For Same
• Brief Description: The ’420 patent discloses methods and apparatus for implementing a resettable memory function in a semiconductor circuit design. The invention addresses the cost and complexity of prior art resettable memories by creating the effect of a reset, such as by using a multiplexer to select between a non-resettable memory's output and a fixed reset value, without requiring the memory cells themselves to be reset.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-2, 10-12, and 20 by Vander Zanden under §102

• Prior Art Relied Upon: Vander Zanden (a 1994 IEEE publication titled “Synthesis of Memories From Behavioral HDLs”).
• Core Argument for this Ground: Petitioner argued that Vander Zanden taught every element of the challenged method and computer-readable media (CRM) claims. The reference described a comprehensive method for synthesizing memory circuits from a high-level behavioral description (e.g., VHDL) into a low-level gate-level design, which inherently involved the claimed steps of "inferring" and "incorporating" a resettable memory.
  • Prior Art Mapping: Petitioner asserted that Vander Zanden taught "inferring the existence of a resetable memory from a behavioral or RTL level description" by describing the synthesis process of identifying a two-dimensional array in VHDL code as a candidate for memory synthesis. The reference's Figure 3 provided a specific example of VHDL code from which a resettable memory is inferred. Vander Zanden taught "incorporating a resetable memory design" by showing the generation of a final gate-level ASIC design (Figure 4) from the behavioral description, which included the inferred resettable memory. The CRM claims were met because Vander Zanden's synthesis method was inherently computer-implemented.

Ground 2: Obviousness of Claims 1-3, 10-13, and 20 over Vander Zanden in view of Shand under §103

• Prior Art Relied Upon: Vander Zanden (IEEE 1994 publication) and Shand (Patent 6,192,447).
• Core Argument for this Ground: Petitioner contended that it would have been obvious to a Person of Ordinary Skill in the Art (POSITA) to combine Vander Zanden’s general memory synthesis methodology with the specific, efficient resettable memory architecture taught by Shand. This combination rendered all challenged claims, including the multiplexer-specific claims 3 and 13, obvious.
  • Prior Art Mapping: Vander Zanden provided the foundational framework for inferring a resettable memory requirement from a behavioral description and synthesizing it into a gate-level design. Shand taught the specific implementation required by claims 3 and 13: a resettable memory comprising a non-resettable memory (RAM), a multiplexer, a reset value input, and a resettable storage cell to control the multiplexer. Shand’s Figure 1 explicitly disclosed this architecture.
  • Motivation to Combine: A POSITA using Vander Zanden's synthesis method would have been motivated to find and incorporate special, optimized architectures like Shand's to achieve "better results." Both references shared the goals of reducing circuit area and delay. Shand explicitly taught a design that provided reset capability with a "small number of additional circuit elements," directly addressing a known design trade-off and providing a clear motivation for its use within Vander Zanden's synthesis process.
  • Expectation of Success: The combination was argued to be predictable and straightforward. Vander Zanden's method was designed to be flexible enough to implement various memory architectures, and Shand's design was entirely compatible with such a synthesis approach.

Ground 3: Obviousness of Claims 1-3, 10-13, and 20 over Vander Zanden in view of Runaldue under §103

• Prior Art Relied Upon: Vander Zanden (IEEE 1994 publication) and Runaldue (Patent 5,067,110).

• Core Argument for this Ground: As an alternative to the Shand combination, Petitioner argued it would have been obvious to combine Vander Zanden’s synthesis method with the resettable memory design taught by Runaldue. Runaldue also provided an efficient, multiplexer-based solution for creating a global reset function for a memory system.

  • Prior Art Mapping: Vander Zanden again supplied the general synthesis method. Runaldue taught the specific hardware for a resettable memory, including a non-resettable memory array, resettable "tag-memory cells" that indicate the reset state of a row, and "zero force logic" (multiplexers) that select between the memory array output and a reset value (e.g., zero). This structure met the limitations of claims 3 and 13.
  • Motivation to Combine: The motivation was similar to that for combining with Shand. A POSITA would seek to implement an optimized architecture like Runaldue's to overcome prior art problems of high circuit area and slow reset times. Runaldue explicitly criticized prior art for requiring external control circuitry and slow, cell-by-cell reset operations, offering a superior solution that a designer using Vander Zanden's method would have been motivated to adopt.
  • Expectation of Success: Petitioner argued there were no technical obstacles to the combination, as Runaldue’s design embodied the principles of building complex memory functions from standard components, an approach fully compatible with Vander Zanden's synthesis framework.

• Additional Grounds: Petitioner asserted additional anticipation challenges against claims 1-2, 10-12, and 20 based on Wohl (a 1999 IEEE publication) and XST (a 2000 Xilinx user guide), both of which described automated synthesis of resettable memories from HDL descriptions. Petitioner also asserted additional obviousness challenges based on combining XST with Shand or Runaldue, relying on similar motivations to implement efficient hardware designs within an automated synthesis tool flow.

4. Key Claim Construction Positions

Petitioner proposed the following constructions under the Broadest Reasonable Interpretation standard:

• resettable memory: "a memory unit whose output value(s) can be cleared to a reset value, e.g., '0', the memory unit comprising one or more storage cells." Petitioner argued this construction was critical because the patent's own disclosure showed embodiments where the memory cells are not actually reset, but only appear to be, which is consistent with prior art multiplexer-based designs.
• inferring: "inferring or recognizing or identifying." Petitioner argued the patent used these terms interchangeably to describe the step of identifying the need for a resettable memory from a high-level circuit description during the synthesis process.
• incorporating: "incorporating or installing." Petitioner asserted this construction was consistent with the patent's language and reflected the well-known EDA step of instantiating a circuit design into a larger gate-level netlist.

5. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-3, 10-13, and 20 as unpatentable.