SanDisk Corp v. Netlist Inc

1. Case Identification

• Case #: IPR2014-00970
• Patent #: 8,001,434
• Filed: June 18, 2014
• Petitioner(s): SanDisk Corporation
• Patent Owner(s): NETLIST, Inc.
• Challenged Claims: 1-35

2. Patent Overview

• Title: Memory Board with Self-Testing Capability
• Brief Description: The ’434 patent relates to a self-testing memory module for testing a plurality of memory devices. The module uses a centralized control module to generate address and control signals and a plurality of distributed, independently operable data handlers to generate test data patterns in local proximity to the memory devices being tested.

3. Grounds for Unpatentability

Ground 1: Anticipation by Averbuj - Claims 1, 14, 15, 17-25, 27, and 29-35 are anticipated by Averbuj under 35 U.S.C. §102(b).

• Prior Art Relied Upon: Averbuj (Application # 2005/0257109).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Averbuj discloses a complete built-in self-test (BIST) architecture that meets every limitation of the challenged claims. Averbuj’s system includes a self-testing memory module on a circuit board, a plurality of memory modules, a sequencer (the claimed "control module") that generates address and control signals, and multiple memory interfaces (the claimed "data handlers"). Petitioner asserted these memory interfaces operate independently to generate test data specific to their corresponding memory modules, thereby teaching the core architecture of the ’434 patent. Averbuj was also argued to disclose the dependent claim limitations, such as using a multiplexer to select between test data and normal operation data and having a comparator to verify test results.

Ground 2: Obviousness over Averbuj and Tsern - Claims 1-12, 14-25, and 27-35 are obvious over Averbuj in view of Tsern.

• Prior Art Relied Upon: Averbuj (Application # 2005/0257109) and Tsern (Application # 2007/0070669).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Averbuj teaches the primary elements of the claims. However, to the extent the Patent Trial and Appeal Board might find Averbuj does not expressly disclose certain low-level implementation details, Tsern supplies them. Specifically, Tsern was cited for its disclosure of a self-testing memory module on a standard printed circuit board (a DIMM) configured to couple to a system memory controller, and its clear illustration of memory devices having separate data, address, and control ports.
  • Motivation to Combine: A POSITA would combine Averbuj’s efficient, distributed BIST architecture with Tsern’s teachings on standard, practical hardware implementations. The motivation was to implement Averbuj's advanced testing logic on a well-known, industry-standard form factor like the DIMM modules disclosed by Tsern to create a commercially viable and efficient product.
  • Expectation of Success: Combining a known testing architecture (Averbuj) with a standard physical layout (Tsern) would have been straightforward for a POSITA and would have yielded a predictable result.

Ground 3: Obviousness over Huang and Tsern - Claims 1-6, 14-16, 19, and 29 are obvious over Huang in view of Tsern.

• Prior Art Relied Upon: Huang (a 2001 IEEE publication) and Tsern (Application # 2007/0070669).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner presented Huang as an alternative primary reference that teaches the core concept of the ’434 patent. Huang describes a transparent BIST method where it is "preferred to have the test interface generate test patterns locally to avoid test data routing from test controller to each memory array." Petitioner argued Huang’s BIST controller is the claimed "control module" and its multiple "transparent memory interfaces" are the claimed "data handlers" that operate independently. As in the previous ground, Tsern was used to supply the allegedly trivial and well-known implementation details of using a printed circuit board, coupling to a memory controller, and having distinct ports on the memory devices.
  • Motivation to Combine: A POSITA would be motivated to implement the efficient, local test-pattern generation method taught by Huang using the standard and practical DIMM module architecture disclosed by Tsern. This combination would achieve the performance benefits described by Huang in a real-world, standardized hardware package.
  • Expectation of Success: A POSITA would have had a high expectation of success in applying Huang's testing logic to the physical memory module structure described in Tsern, as it involved combining a known testing method with a standard hardware platform.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Averbuj, Tsern, and the JEDEC Standard to teach storing failure data and addresses. Further grounds combined Huang, Tsern, and Averbuj to teach elements like generating cyclic data and performing read-back verification.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-35 of the ’434 patent as unpatentable.