PTAB

IPR2014-01105

Texas Instruments Inc v. Vantage Point Technology Inc

Log In
Key Events
Petition
petition Intelligence

1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Virtual-to-Real Address Translation
  • Brief Description: The ’750 patent discloses a method and apparatus for translating virtual addresses to real addresses in a computing system with multiple instruction pipelines. The invention’s core concept is the use of a separate translation lookaside buffer (TLB) for each instruction pipeline to improve performance and reduce memory access conflicts, which were a known disadvantage in conventional systems that used a single, shared TLB for all pipelines.

3. Grounds for Unpatentability

Ground 1: Claims 8-14 are obvious over AAPA in view of Kubo

  • Prior Art Relied Upon: AAPA (Applicant Admitted Prior Art from the ’750 patent) and Kubo (Patent 4,618,926).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that AAPA described a conventional computing system having multiple instruction pipelines that shared a single TLB. The AAPA itself acknowledged the performance “disadvantages when a single memory array is used to service address translation requests from multiple pipelines.” Kubo, in contrast, disclosed a buffer control system for a processor that used separate TLBs for different operation types—a fetch/load TLB (FTLB) and a store TLB (STLB)—to reduce competition and improve performance. Petitioner contended that the combination of these references taught all elements of the challenged claims.
    • Motivation to Combine: A POSITA would combine the separate TLB architecture of Kubo with the multi-pipeline system described in AAPA. The motivation was explicit and compelling: to solve the precise problem of memory access competition that AAPA identified as a known disadvantage in the art. Kubo provided a known solution (separate buffers) for this exact problem.
    • Expectation of Success: The combination involved applying a known technique from Kubo to a known system from AAPA to achieve the predictable result of improved performance by reducing pipeline conflicts. Petitioner asserted this was a straightforward design choice with a high expectation of success.

Ground 2: Claim 8 is anticipated by the Clipper Paper

  • Prior Art Relied Upon: Cho et al., “The Memory Architecture and the Cache and Memory Management Unit for the Fairchild CLIPPER processor,” Tech. Report UCB/CSD 86/289 (Apr. 1986) (“Clipper Paper”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that the Clipper Paper disclosed a processor architecture that anticipated every limitation of claim 8. The Clipper Paper described a module with two identical, separate cache and memory management units (CAMMUs)—one for instructions and one for data. Petitioner mapped these two CAMMUs to the claimed "first and second instruction pipelines." Each CAMMU included its own TLB and its own Dynamic Translation Unit (DTU). The system’s main memory functioned as the “master translation memory.” Under an alternative construction where the "direct address translation unit" could comprise multiple components, Petitioner argued the collective DTUs and main memory of the Clipper system met this limitation.
    • Key Aspects: This anticipation ground was presented as an alternative argument, contingent on the Board rejecting Petitioner’s proposed construction of "direct address translation unit" as a single, shared unit. Petitioner argued that the Clipper architecture was nearly identical to the accused architecture in parallel district court litigation, invoking the principle that a device which infringes if later, anticipates if earlier.

4. Key Claim Construction Positions

  • "master translation memory": Petitioner contended this term should be construed as “main memory.” This construction was based on the specification’s explicit statements that page tables are “typically stored in main memory” and that the update control circuit stores translation data “retrieved from the main memory into the TLB.”
  • "direct address translation unit": Petitioner proposed this term should be construed as a “single dynamic translation unit” and “main memory.” This construction was central to the petition’s primary obviousness argument. Petitioner argued that the specification and figures of the ’750 patent consistently depicted a single, shared Dynamic Translation Unit (DTU) that serves multiple pipelines upon a TLB miss. This shared nature was asserted as a key feature of the claimed invention, distinct from the dedicated TLB for each pipeline.

5. Relief Requested

  • Petitioner requests institution of inter partes review (IPR) and cancellation of claims 8-14 of Patent 5,463,750 as unpatentable.