PTAB

IPR2014-01159

ATopTech Inc v. Synopsys Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Physically Designing an Integrated Circuit
  • Brief Description: The ’967 patent discloses a method for the physical design of large integrated circuits (ICs) by partitioning a hierarchical netlist into multiple independent place and route units (PRUs). The invention addresses inter-PRU routing and timing by using temporary "dummy ports" and allocating "slack time" between the PRUs.

3. Grounds for Unpatentability

Ground 1: Anticipation/Obviousness of Claim 31 over Ling

  • Prior Art Relied Upon: Ling (Patent 6,223,329).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ling discloses a complete hierarchical design methodology that anticipates or, in the alternative, renders obvious every element of claim 31. Ling’s method involves flattening hierarchical blocks, routing global networks through them using temporary pin/port assignments, and then decoupling the blocks for independent final routing. Petitioner asserted this process directly maps to claim 31’s steps of: (1) creating temporary "dummy ports" on PRUs; (2) connecting the dummy ports by routing nets; (3) determining where the nets cross PRU edges; (4) deleting the dummy ports; and (5) generating "real ports" at the final crossing locations.
    • Motivation to Combine (for §103 grounds): The motivation was inherent in Ling's disclosure, which aimed to solve the known problem of global routing in hierarchical designs by decoupling blocks to allow for independent processing.

Ground 2: Claims 5-6 and 23-26 are obvious over Fields in view of Su and Ling

  • Prior Art Relied Upon: Fields (a 1995 conference paper on HDL-based design), Su (a 1998 symposium paper on soft-macro clustering), and Ling (Patent 6,223,329).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Fields and Su together teach the foundational method of partitioning and placing atomic blocks within PRUs, while Ling provides the necessary teachings for inter-PRU routing recited in the dependent claims. Fields was cited for its method of partitioning a large, hierarchical design into mid-size modules (atomic blocks) and constraining them into physical regions (PRUs). Su was argued to supplement Fields by teaching the specific placement of hard and soft macro blocks within a PRU. Ling was then combined to supply the specific inter-PRU routing techniques, such as creating dummy ports on soft and hard blocks to manage connections between PRUs, as recited in claims 5-6 and 23-26.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Fields and Su as they address complementary aspects of hierarchical IC design. Having created a partitioned floorplan per Fields and Su, the POSITA would face the well-known problem of routing signals between the partitions. A POSITA would have been motivated to look to known solutions like Ling's method for decoupling blocks and managing inter-block routing with temporary ports.
    • Expectation of Success: Combining these known techniques for partitioning (Fields), placement (Su), and inter-block routing (Ling) was presented as a predictable integration of solutions to solve a common, complex design problem.

Ground 3: Claims 27-30 are obvious over Fields in view of Su and Venkatesh

  • Prior Art Relied Upon: Fields (a 1995 conference paper), Su (a 1998 symposium paper), and Venkatesh (Patent 5,778,216).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground uses the same Fields/Su combination as the base method for partitioning and placement but adds Venkatesh to address the "slack time" limitations recited in claims 27-30. Petitioner argued that Venkatesh explicitly teaches a hierarchical, timing-driven layout method that includes a "timing budgeter." This system distributes timing slack to nets connecting the partitioned blocks, which directly corresponds to the limitations in claims 27-30 concerning allocating slack time to PRUs, including allocation primarily to input or output pins.
    • Motivation to Combine: A POSITA implementing the hierarchical physical design flow taught by Fields and Su would necessarily need to manage timing constraints and slack, a critical and inherent challenge in IC design. Petitioner asserted that a POSITA would have been motivated to incorporate a known, compatible timing and slack allocation methodology, such as the one taught by Venkatesh, into the overall design process.
    • Expectation of Success: Integrating a standard timing analysis and slack allocation method from Venkatesh into the hierarchical partitioning and placement flow from Fields/Su would have been a straightforward and predictable task for a POSITA, with a high expectation of success.

4. Key Claim Construction Positions

  • "Place and Route Unit (PRU)": Petitioner proposed this term means "sections created to represent the physical partitioning of the IC design." This construction asserts that a PRU is simply a section of the IC, not limited by its specific method of creation, allowing art that partitions a chip into physical regions to qualify as teaching PRUs.
  • "Dummy Port": Petitioner defined this as a "temporary placement of the starting and ending points for routing nets between PRUs." This construction is critical for mapping Ling’s disclosure of temporary pin assignments onto the "dummy port" limitations of the ’967 patent.
  • "Partitioning": Petitioner proposed this term means "dividing up a logical representation of a circuit design into physically realizable sections... to create an additional level of hierarchy." This supports the argument that Fields’s method of re-grouping modules into new, larger modules constitutes the claimed "partitioning" step.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 5-6 and 23-31 as unpatentable.