PTAB

IPR2014-01369

Smart Modular Technologies Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System And Method Utilizing Distributed Byte-Wise Buffers On A Memory Module
  • Brief Description: The ’185 patent discloses a memory module architecture designed to reduce memory load. The system uses a single on-board controller for control and address signals, and multiple distributed data transmission circuits to selectively manage data flow between a system memory controller and memory devices.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-19 by Gower

  • Prior Art Relied Upon: Gower (Patent 7,865,674).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Gower discloses every limitation of the challenged claims. Gower’s memory module includes a link interface (504) that functions as the claimed "controller" by receiving signals from an external memory controller and producing address/command information. Multiple memory hub controllers (502, 604, 606), which include multiplexers and data queues, constitute the claimed "plurality of circuits." Critically, Gower discloses circuits with 8-byte wide data buses that interface with memory devices (506) having a smaller 4-bit wide configuration, meeting the bit-width limitation. The data queues (522, 528) function as the claimed read/write buffers, and the multiplexers (540, 541, 550) allow for the selective data transmission and isolation required by the claims.
    • Key Aspects: Gower’s disclosure of circuits with wider data buses than their corresponding memory devices was a central point of the anticipation argument.

Ground 2: Anticipation of Claims 1-19 by Tsern

  • Prior Art Relied Upon: Tsern (Patent 7,464,225).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended Tsern also anticipates all claims. Tsern discloses a memory module (800) with an address/control buffer (501) that serves as the "controller" and multiple data buffers (100a-d) that serve as the "plurality of circuits." Tsern explicitly teaches that its data buffers have a configurable bit width, which can be set wider than the bit width of the memory devices (101) they are connected to, thus satisfying the key bit-width limitation. The buffers (100) are disclosed with a cache (1860) containing write and read buffers, and they use multiplexers to selectively allow and isolate data from an external processor, mapping to the functional requirements of the claims.
    • Key Aspects: The argument centered on Tsern’s teaching of a configurable bit width for its buffers, allowing them to be wider than the memory devices, and its use of a cache and multiplexers to perform the claimed buffering and isolation functions.

Ground 3: Obviousness of Claims 1-19 over Best in view of Tsern

  • Prior Art Relied Upon: Best (Patent 8,233,303) and Tsern (Patent 7,464,225).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Best discloses most claim elements and Tsern supplies the remainder, making the combination obvious. Best discloses a memory module with an on-module subsystem memory controller (870) that functions as the claimed "controller" and multiple interface dies (421) that function as the "plurality of circuits." Best's interface dies have a 16 or 32-bit width and connect to memory arrays with a smaller 8-bit width, meeting the bit-width limitation. Best also discloses storage buffers that function as read/write buffers. Tsern was cited to provide teachings on adapting the controller to receive signals from an external master processor and provide module control signals to the interface dies, as taught by Tsern's buffer (501).
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Best and Tsern because the published application for Tsern was cited during the prosecution of Best. Furthermore, both references address similar problems by using an intermediate buffer or interface die in a stacked memory configuration, suggesting a natural and logical combination to achieve the claimed invention.
    • Expectation of Success: The combination involved applying known techniques (Tsern's controller signaling) to a known system (Best's memory module) to achieve a predictable result, giving a POSITA a reasonable expectation of success.

4. Key Claim Construction Positions

  • "operable" / "operatively coupled": Petitioner proposed this term means "capable of operating together," arguing for a broad interpretation based on the specification and standard technical dictionaries. This construction supports finding the limitation met when circuits are associated in a way that allows power or signal information to be transferred.
  • "selectively isolate": Petitioner argued this means "electrically separating the input of a component from the output of another component using high impedance." This construction, based on the patent’s description of seeing a "single load," was used to argue that the multiplexers and data queues in the prior art, which can be switched to a high-impedance state, perform this function.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-19 of the ’185 patent as unpatentable.