PTAB

IPR2014-01370

Smart Modular Technologies Inc v. Netlist Inc

Key Events

Petition

petition

Title: NON-VOLATILE MEMORY MODULE
Brief Description: The ’833 patent discloses a hybrid memory system comprising a volatile memory subsystem (e.g., DRAM) and a non-volatile memory subsystem (e.g., flash memory). The system operates in at least two modes: a high-speed mode for communication between the volatile memory and a host system, and a lower-speed mode for internal data communication between the volatile and non-volatile subsystems, such as for backup operations.

Prior Art Relied Upon: Fukuzo (Application # 2006/0294295).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Fukuzo discloses every limitation of independent claims 1 and 15. Fukuzo describes a memory device with a volatile SDRAM buffer and a non-volatile flash memory subsystem. It explicitly teaches operating the SDRAM buffer at a first, higher clock frequency (130 MHz) when communicating with a host CPU (first mode of operation) and operating both the SDRAM buffer and the flash memory at a second, lower clock frequency (20 MHz) during internal data transfers between them (second mode of operation). Because the 20 MHz clock frequency is less than the 130 MHz frequency, Fukuzo was alleged to teach all limitations of the independent claims. Petitioner further mapped Fukuzo's disclosures of command signals, on-board components, and backup/restore operations to the various dependent claims.

Prior Art Relied Upon: Fukuzo (Application # 2006/0294295) and Leete (Application # 2004/0190210).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Fukuzo teaches the base hybrid memory system as outlined in Ground 1. Leete was introduced to supply limitations missing from Fukuzo for certain dependent claims. Specifically, Leete discloses using a capacitor to provide backup power in a reduced power mode, which allegedly renders obvious claim 3 (not powered by a battery in the second mode). Leete also teaches detecting a power failure condition to trigger a backup, allegedly rendering obvious claim 5.
- Motivation to Combine: A POSITA would combine Fukuzo and Leete because both address the known problem of data backup in DRAM-Flash systems during reduced power or power-loss events. A POSITA would have found it obvious to implement the capacitor-based backup power solution from Leete into the hybrid memory system of Fukuzo to achieve a predictable, reliable power source for backup operations.
- Expectation of Success: A POSITA would have a high expectation of success, as combining a known power backup method (capacitor power from Leete) with a standard hybrid memory architecture (Fukuzo) involves the application of known technologies to yield predictable results.

Prior Art Relied Upon: Ichikawa (Patent 7,600,142).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Ichikawa, like Fukuzo, discloses all elements of the independent claims. Ichikawa describes a memory device with volatile RAM and a non-volatile flash memory system. The system operates the RAM at a first clock frequency (5 MHz) for communications with a host CPU and at a second, lower clock frequency (1 MHz) for communications with the flash memory during a power-saving mode. This two-mode, two-speed operation was asserted to meet the limitations of independent claims 1 and 15. Petitioner also contended that Ichikawa’s teachings on data saving processes and configurable clock signals anticipated several dependent claims.
Additional Grounds: Petitioner asserted additional anticipation and obviousness challenges based on Long (’552 patent) and Tsunoda (’618 patent), each individually and in combination with Leete. These arguments relied on similar theories that these references also disclose hybrid memory systems with dual clock-speed operating modes and that Leete provides obvious modifications for power management and backup initiation.

"operatively coupled" (claims 1, 15): Petitioner proposed this term be construed as "capable of operating together." This broad construction was argued to be consistent with the specification and dictionary definitions, and it facilitates finding the limitation met where components are connected to transfer signals or power.
"memory subsystem" (claims 1, 15, et al.): Petitioner proposed this term be construed as "two or more memory components." This construction was based on language in the specification describing subsystems as comprising a "plurality" of memory elements and was important for arguing that prior art showing multiple memory chips or components meets this limitation.

Petitioner argued that it was not barred from filing the petition under §315(a)(1) despite having previously filed a district court complaint for declaratory judgment regarding the ’833 patent. Petitioner noted that the district court case was dismissed without prejudice. Citing PTAB precedent, Petitioner contended that a civil action dismissed without prejudice is treated as if it never existed, and therefore the one-year statutory bar of §315(a)(1) was not triggered.

Petitioner requests institution of an inter partes review and cancellation of claims 1-30 of the ’833 patent as unpatentable.