PTAB

IPR2014-01372

Smart Modular Technologies Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Board With Self-Testing Capability
  • Brief Description: The ’434 patent discloses a self-testing memory module utilizing Built-In Self-Test (BIST) circuitry. The invention describes a specific BIST configuration comprising a control module to generate address and control signals, and a plurality of independently operable data handlers coupled to the data ports of memory devices to generate and verify test data.

3. Grounds for Unpatentability

Ground 1: Anticipation over Averbuj - Claims 1-4, 14-20, 27, and 29 are anticipated by Averbuj under 35 U.S.C. §102.

  • Prior Art Relied Upon: Averbuj (Patent 7,392,442).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Averbuj discloses every element of the challenged independent claims. Averbuj’s BIST architecture for an electronic device was asserted to be a "self-testing memory module" comprising a printed circuit board with memory devices. Petitioner mapped Averbuj’s "BIST controller" to the claimed "control module" and its pairs of "sequencers" and "memory interfaces" to the claimed "plurality of data handlers." Averbuj’s disclosure that each sequencer controls application speed according to its corresponding memory component was argued to meet the "operable independently" limitation.
    • Key Aspects: Petitioner contended that Averbuj’s data generation unit, which creates the exact data applied to memory inputs, directly teaches the limitation of generating data for writing to the memory devices’ data ports.

Ground 2: Obviousness over Averbuj and Best - Claims 5-7, 13, 21, 26, 28, 30, and 35 are obvious over Averbuj in view of Best.

  • Prior Art Relied Upon: Averbuj (Patent 7,392,442) and Best (Patent 8,233,303).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Averbuj taught the foundational BIST system, as detailed in Ground 1. Best was introduced to teach the physical placement of BIST circuitry. Specifically, Best discloses a multi-die memory device where a BIST-enabled interface die is positioned in "close proximity" to the wire terminals of a storage die. This combination was argued to render obvious claims requiring data handlers to be positioned "proximate" to the corresponding data ports (claim 5) or "closer" to their corresponding ports than to others (claim 6).
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Averbuj's BIST architecture with Best's proximate interface die placement. The motivation was to incorporate a known BIST solution into a modern multi-die memory module to gain the predictable benefits of improved signal integrity and reduced latency, which result from placing testing circuitry close to the components being tested.
    • Expectation of Success: The combination of these known elements for their established purposes would have yielded predictable results, giving a POSITA a reasonable expectation of success.

Ground 3: Obviousness over Rajan and Averbuj - Claims 1-7, 13-21, 26-30, and 35 are obvious over Rajan in view of Averbuj.

  • Prior Art Relied Upon: Rajan (Patent 7,379,316) and Averbuj (Patent 7,392,442).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Rajan discloses the structural framework of the invention: a Fully Buffered DIMM (FBDIMM) memory module with an Advanced Memory Buffer (AMB) chip and stacked memory chips. Petitioner mapped Rajan’s AMB chip to the "control module" and the interface chip included in each memory stack to a "data handler." Averbuj was then relied upon to supply the specific BIST functionality, including its detailed BIST controller and sequencer/memory interface operations, which could be implemented within Rajan's framework.
    • Motivation to Combine: A POSITA would have been motivated to implement the known, detailed BIST architecture from Averbuj into the FBDIMM architecture of Rajan. This would add robust self-testing capabilities to Rajan’s more advanced memory module design, a well-understood and desirable enhancement for complex electronic systems.
    • Expectation of Success: Implementing a known testing methodology (Averbuj) into a known memory structure (Rajan) was a straightforward application of existing technologies that would have provided a high expectation of success.
  • Additional Grounds: Petitioner asserted further obviousness challenges by adding Pandey (Patent 6,934,205) to the Averbuj/Best and Rajan/Averbuj combinations. Pandey was primarily used to teach a verification element (comparator) that generates expected data on-the-fly for comparison, thereby obviating the need to store a copy of the written test data.

4. Key Claim Construction Positions

  • "proximate" (claims 5 and 28): Petitioner argued this term is not indefinite if construed to mean positioned close enough to the corresponding data ports to achieve a functional purpose, such as reducing latency. However, Petitioner asserted that if the term is given its broadest reasonable interpretation to mean anywhere on the printed circuit board, then the claims would be indefinite under 35 U.S.C. §112 for failing to inform a POSITA of the claim scope with reasonable certainty. This construction was central to Ground 6, an alternative indefiniteness challenge.
  • "operable independently" (claims 1, 27, and 29): Petitioner proposed this term means "capable of operating in the absence of signals therebetween," citing specification language that data handlers can operate "without being in communication [with] any of the other data handlers." This construction supported the argument that Averbuj's sequencers, which operate based on the speed of their respective memory components, meet the limitation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-35 of the ’434 patent as unpatentable.