Smart Modular Technologies Inc v. Netlist Inc

1. Case Identification

• Case #: To be assigned (A related petition, IPR2014-00970, was filed by SanDisk Corporation)
• Patent #: 8,001,434
• Filed: August 22, 2014
• Petitioner(s): SMART Modular Technologies, Inc.
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 1-35

2. Patent Overview

• Title: Memory Board with Self-Testing Capability
• Brief Description: The ’434 patent relates to systems and methods for Built-In Self-Test (BIST) of memory modules. The invention describes a specific BIST circuit configuration on a memory module, comprising a control module to generate test signals and a plurality of independently operable data handlers to generate and manage test data for the memory devices.

3. Grounds for Unpatentability

Ground 1: Obviousness over Fleischman and JTAG - Claims 1-35 are obvious over Fleischman in view of JTAG 2001.

• Prior Art Relied Upon: Fleischman (Patent 6,321,320) and JTAG 2001 (IEEE Standard 1149.1-2001).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Fleischman discloses a BIST architecture for integrated circuits with all the key elements of the challenged claims, including a BIST main control and address generator (the claimed "control module") and multiple, independently controlled data generation units (the claimed "plurality of data handlers"). However, Fleischman teaches these components on an IC chip. JTAG 2001, a well-known industry standard, explicitly teaches the application of BIST architectures, like that in Fleischman, to populated printed circuit boards (PCBs). Therefore, implementing Fleischman's JTAG-compliant BIST system on a PCB as taught by JTAG 2001 would arrive at the claimed self-testing memory module.
  • Motivation to Combine: A POSITA would combine Fleischman and JTAG 2001 because Fleischman expressly discloses compliance with the JTAG standard. JTAG 2001 defines the standard environment for applying such self-test architectures to devices on a PCB. The combination would be a straightforward adaptation of Fleischman's known BIST architecture to the standard PCB environment defined by JTAG 2001 to achieve the predictable result of on-board memory testing.
  • Expectation of Success: A POSITA would have a high expectation of success as it involves applying a BIST architecture (Fleischman) in the exact type of JTAG-compliant PCB environment for which it was designed and which is described by the JTAG 2001 standard.

Ground 2: Obviousness over Adams and JTAG - Claims 1-7, 13-21, 26-30, and 35 are obvious over Adams in view of JTAG 2001.

• Prior Art Relied Upon: Adams (Patent 7,203,873) and JTAG 2001 (IEEE Standard 1149.1-2001).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Adams, like Fleischman, discloses a JTAG-compliant BIST architecture for testing memory devices. Adams teaches an MBIST controller (the claimed "control module") and multiple, independently enabled "collar" circuits that surround the memory devices (the claimed "plurality of data handlers"). Each collar includes a data generator to test its corresponding memory device. As with the first ground, JTAG 2001 provides the necessary disclosure of implementing such a system on a PCB.
  • Motivation to Combine: The motivation is direct, as Adams explicitly states its BIST architecture is applicable to any JTAG-compliant environment. A POSITA would be motivated to adapt the BIST architecture of Adams to a PCB in accordance with the well-known JTAG 2001 standard to leverage existing, standardized testing protocols and equipment.
  • Expectation of Success: Success would be expected because the combination merely implements the BIST system of Adams in the standard JTAG-compliant PCB environment that Adams was designed for and that JTAG 2001 details.

Ground 3: Obviousness over Adams, JTAG, and Huang - Claims 8-12, 22-25, and 31-34 are obvious over Adams in view of JTAG 2001 and Huang 2000.

• Prior Art Relied Upon: Adams (Patent 7,203,873), JTAG 2001 (IEEE Standard 1149.1-2001), and Huang 2000 (an IEEE technical paper titled "An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers").
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground 2 by adding Huang to address limitations related to data verification, specifically those requiring calculation of comparison data without storing a copy of the test pattern. Adams and JTAG 2001 establish the base self-testing module. Huang discloses using a Multi-Input Shift Register (MISR) with comparator logic to generate expected data and compare it with data read from memory in real-time. This method, taught by Huang, satisfies the limitations requiring a "verification element" that "calculates comparison data" without storing the written data beforehand.
  • Motivation to Combine: A POSITA would be motivated to incorporate Huang’s efficient verification method into the Adams/JTAG framework to improve the BIST system. Huang and Adams disclose similar BIST architectures with local test data generators. A POSITA would recognize that Huang’s transparent interface and MISR-based comparison logic could be readily replicated within the collar logic of Adams to create a more efficient test system that avoids routing all test data back to a central controller, a known design goal.
  • Expectation of Success: A POSITA would expect success in combining these references because it involves integrating a known, efficient data verification technique (Huang) into a standard, compatible BIST architecture (Adams/JTAG).

4. Key Claim Construction Positions

• "operatively coupled": Petitioner proposed the construction "capable of operating together," arguing for a broad interpretation that includes logical and/or electrical connections.
• "data module": Proposed as a "group or set of data components," supported by dictionary definitions and intrinsic evidence.
• "proximate": Petitioner argued that under the broadest reasonable interpretation, "proximate" could mean anywhere on the printed circuit board. Petitioner further argued that if this construction is not adopted, the term is indefinite under §112 because it fails to inform a POSITA with reasonable certainty about the required location of the data handlers, rendering claims 5, 6-13, and 28 unpatentable.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that it is not barred from filing the IPR petition under §315(a)(1) despite having previously filed a declaratory judgment action against the Patent Owner regarding the ’434 patent. The basis for this argument was that the district court action was dismissed without prejudice. Citing PTAB precedent (e.g., Clio USA, Inc.), Petitioner contended that a dismissal without prejudice is a legal nullity, meaning the action is treated as if it never existed, and thus the one-year statutory bar of §315(a)(1) was not triggered.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-35 of the ’434 patent as unpatentable.