PTAB

IPR2014-01375

Smart Modular Technologies Inc v. Netlist Inc

Key Events

Petition

petition

Title: Memory Board With Self-Testing Capability
Brief Description: The ’501 patent relates to memory modules with Built-In Self-Test (BIST) capabilities. The disclosed invention concerns a specific configuration of on-board BIST circuitry designed to test memory devices, featuring a control circuit and a plurality of independently operated data handlers.

Prior Art Relied Upon: Fleischman (Patent 6,321,320) and JTAG 2001 (IEEE Standard No. 1149.1-2001).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Fleischman discloses a BIST architecture for an integrated circuit that includes all key elements of the claimed invention. Specifically, Fleischman’s BIST main control and address generation unit constitute the claimed “control circuit,” and its multiple, separately controlled Data Data Generation (DDG) units are the claimed “plurality of data handlers.” JTAG 2001 was cited as providing the standard industry framework for applying such BIST architectures to memory devices on a printed circuit board (PCB), thus creating the claimed “memory system.”
- Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references because Fleischman expressly states that its architecture is designed for compliance with the JTAG standard. Petitioner contended that JTAG 2001 simply provides the well-known environment (a PCB with standardized test access) for which the Fleischman BIST system was intended, making the combination a predictable application of known technologies.
- Expectation of Success: A POSITA would have had a high expectation of success, as combining a JTAG-compliant device with the JTAG standard itself represents a routine implementation rather than an inventive step.

Prior Art Relied Upon: Adams (Patent 7,203,873) and JTAG 2001 (IEEE Standard No. 1149.1-2001).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Adams discloses a BIST environment with an MBIST controller that functions as the claimed “control circuit” and multiple “collar” logic devices surrounding memory devices that function as the claimed “plurality of data handlers.” Adams further teaches that these collars can be selectively enabled for testing, which Petitioner argued meets the limitation of being “operated independently.” As in Ground 1, JTAG 2001 was presented as teaching the application of such a BIST system to a PCB.
- Motivation to Combine: The motivation was argued to be explicit, as Adams states its BIST architecture is applicable to any JTAG-compliant environment. A POSITA would naturally look to the JTAG 2001 standard to implement the Adams system on an assembled PCB, which is a common application for memory modules.
- Expectation of Success: The combination was argued to be a predictable integration of a system (Adams) designed for a particular standard (JTAG 2001), which would have been straightforward for a POSITA.

Prior Art Relied Upon: Adams (’873 patent), JTAG 2001 (IEEE Standard No. 1149.1-2001), and Huang 2000 (“An Efficient Parallel Transparent BIST Method for Multiple Embedded Memory Buffers,” IEEE, 2000).
Core Argument for this Ground:
- Prior Art Mapping: This ground builds upon the Adams/JTAG 2001 combination to address specific dependent claims requiring verification of read data “without storing a copy of the data generated and written.” Petitioner argued that Huang teaches exactly this functionality through its disclosure of a Multi-Input Shift Register (MISR). Huang’s MISR generates expected data on-the-fly during a read operation for immediate comparison, obviating the need to store the original test pattern. This technique directly maps to the limitations of the challenged dependent claims.
- Motivation to Combine: A POSITA would combine Huang’s efficient verification method with the Adams/JTAG 2001 system to improve BIST performance and reduce memory overhead, which are known design goals. Huang’s technique of using a local data generator and comparator is analogous to the distributed “collar” architecture in Adams, making the integration logical and beneficial.
- Expectation of Success: Integrating a known data comparison technique (Huang) into a standard BIST architecture (Adams) would be a predictable design choice with a high expectation of success for a POSITA seeking to optimize memory testing.

"operatively coupled" (Claims 1, 16): Petitioner proposed the construction “capable of operating together.” This construction was argued to be consistent with the specification and necessary to establish the fundamental connection between the claimed memory system and an external computer system’s memory controller.
"operated independently" (Claims 1, 16): Petitioner proposed the construction “capable of operating in the absence of signals therebetween.” This construction was critical to Petitioner's arguments that the distributed test units in the prior art (e.g., Fleischman's DDGs and Adams's collars), which are controlled separately but may share common clock or control signals, still meet the claim limitation.

Petitioner argued that the petition was not time-barred under 35 U.S.C. §315(a)(1), despite having previously filed a declaratory judgment action regarding the ’501 patent. Petitioner asserted that because the district court action was dismissed without prejudice, it is treated as a legal nullity (“as if the complaint never existed”). Therefore, Petitioner contended it was not statutorily barred from filing the IPR petition.

Petitioner requested the institution of an inter partes review and the cancellation of claims 1-20 of Patent 8,359,501 as unpatentable under 35 U.S.C. §103.