PTAB

IPR2014-01567

Apple Inc v. Wisconsin Alumni Research Foundation

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Data Speculation Circuit for a Computer Processor
  • Brief Description: The ’752 patent discloses a method and apparatus for improving performance in an out-of-order microprocessor by using a predictor to determine whether to speculatively execute instructions. The system specifically addresses data dependencies, such as when a "load" instruction (data consuming) depends on an earlier "store" instruction (data producing), by predicting the likelihood of a "mis-speculation" and delaying execution if necessary.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hesson in view of Steely - Claims 1-9 are obvious over Hesson in view of Steely.

  • Prior Art Relied Upon: Hesson (Patent 5,666,506) and Steely (Patent 5,619,662).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hesson disclosed a processor with every element of independent claim 1 except for one: associating the prediction with the particular data consuming instruction (e.g., a load instruction). Hesson’s predictor, a "store barrier cache" that uses "history bits" to track mis-speculations, associated its prediction only with the data producing instruction (e.g., a store instruction). Petitioner asserted that Hesson's "writeback unit" functions as the claimed "data speculation circuit" for detecting mis-speculations (termed "store violation conditions" in Hesson), and its "rename unit" and "reservation station" function as the "prediction threshold detector" for preventing data speculation. Steely was argued to supply the missing element.
    • Motivation to Combine (for §103 grounds): Petitioner contended a person of ordinary skill in the art (POSITA) would combine Hesson and Steely because both address the same problem in the same field: predicting and managing data dependencies in out-of-order processors to improve performance. The motivation stemmed from improving Hesson's efficiency. Hesson's system, upon predicting a mis-speculation for a store instruction, delayed all subsequent load instructions. Steely taught a more granular approach, basing predictions on specific load-store pairs. A POSITA would have been motivated to modify Hesson's predictor to incorporate Steely's technique to delay only the specific load instruction involved in a prior mis-speculation, thereby avoiding unnecessary stalls and increasing overall processor speed.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because the modification was a predictable design choice. It involved adding a field to Hesson's store barrier cache to store the address of the specific load instruction, a straightforward change well within the skill of an ordinary artisan. This modification represented a known trade-off between increased cache size and improved performance.
    • Key Aspects: The core of the argument was that applying Steely’s more precise method of tracking problematic instruction pairs to Hesson’s architecture was an obvious improvement to solve a known performance bottleneck. Petitioner further argued that the dependent claims (2-8) added limitations that were also taught by Hesson, either alone or as modified by Steely. For example, claim 3's "prediction table" was mapped to Hesson's store barrier cache as modified by Steely, and claim 8's "tallying" was mapped to Hesson's use of incrementing history bits upon each mis-speculation. Claim 9 was addressed as being substantively identical to claim 1, with its limitations rendered obvious by the same combination.

4. Key Claim Construction Positions

  • "predictor": Petitioner proposed the construction "a circuit that receives a mis-speculation indication from the data speculation circuit to produce a prediction." This construction was argued to be supported by the plain language of claim 1 and was critical for mapping the term to Hesson's "store barrier cache," which receives indications of "store violation conditions" (mis-speculations) to update its history bits.
  • "prediction": Petitioner proposed the construction "a value that indicates the likelihood that the data speculative execution of a data consuming instruction will result in a mis-speculation." This construction was essential for arguing that Hesson's multi-bit "history bits," which are incremented or decremented based on past performance, constituted the claimed "prediction," as their value directly corresponds to the likelihood of a future conflict.
  • "mis-speculation": Petitioner proposed the construction "when a data consuming instruction that is dependent for its data on a data producing instruction appearing earlier in the program order is in fact executed before the data producing instruction." This construction equated the patent's term with the well-understood "store violation condition" described in Hesson, linking the prior art directly to the claimed problem and solution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of the ’752 patent as unpatentable.