PTAB

IPR2014-01567

Apple Inc. v. Wisconsin Alumni Research Foundation

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1. Case Identification

2. Patent Overview

  • Title: Processor with a Predictor for Speculative Instruction Execution
  • Brief Description: The ’752 patent relates to improving performance in microprocessors capable of "out-of-order" execution. The invention is a method and apparatus, using a predictor, to determine whether to speculatively execute a "data consuming" instruction (e.g., a load) before a "data producing" instruction (e.g., a store) on which it may depend, thereby avoiding potential processing delays while managing the risk of errors from mis-speculation.

3. Grounds for Unpatentability

Ground 1: Claims 1-9 are obvious over Hesson in view of Steely.

  • Prior Art Relied Upon: Hesson (Patent 5,666,506) and Steely (Patent 5,619,662).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Hesson discloses nearly every element of the challenged claims. Hesson teaches a processor that performs out-of-order execution and uses a predictor to avoid data dependency errors. Specifically, Hesson’s "store barrier cache" functions as a predictor, using "history bits" (the claimed "prediction") to track past "store violation conditions" (the claimed "mis-speculation"). When a store instruction is identified as likely to cause a violation, Hesson’s "rename unit" (the claimed "prediction threshold detector") prevents dependent load instructions from executing prematurely.

      Petitioner contended that Hesson’s system had one key distinction from the ’752 patent: its prediction is associated only with the store (data producing) instruction. When a potential mis-speculation is predicted, Hesson delays all subsequent load instructions, not just the specific one that is actually dependent.

      Petitioner asserted that Steely remedies this sole deficiency. Steely, which addresses the same problem of predicting load-store dependencies, explicitly teaches associating a prediction with a pair of instructions: the specific data consuming (load) and data producing (store) instructions that previously caused a mis-speculation. By using tags that identify the specific load-store pair, Steely’s system avoids speculatively reordering only that specific pair, allowing other, non-dependent instructions to proceed.

      The combination of Hesson's prediction architecture with Steely's more precise method of associating predictions to specific load-store pairs allegedly renders independent claim 1 obvious. Petitioner further argued this combination teaches the limitations of the other challenged claims. For example, Hesson’s rename unit and reservation station function as the "instruction synchronization circuit" (claims 2, 3, 5, 9), and its store barrier cache, when modified by Steely to store both load and store addresses, becomes the claimed "prediction table" (claims 3, 4, 9) or "synchronization table" (claim 5).

    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to combine Hesson and Steely to improve performance. Both patents are in the same field, address the identical problem, and use similar history-based prediction solutions. Hesson’s approach of stalling all subsequent loads is a coarse, inefficient solution. Steely teaches a more granular and efficient solution by targeting only the specific load instruction involved in a potential conflict. A POSITA would have recognized that incorporating Steely's precision into Hesson's framework was a predictable design improvement to increase processing speed by avoiding unnecessary stalls. This was one of a finite number of known, predictable solutions to the problem.

    • Expectation of Success: A POSITA would have had a high expectation of success in this combination. Modifying Hesson's cache to also store the address of the relevant load instruction—as taught by Steely—was a routine design task. The choice between associating a prediction with a store instruction, a load instruction, or a load-store pair was a well-understood design trade-off between hardware complexity (storage space) and performance. Implementing this known, superior method would have been a straightforward modification with predictable results.

4. Key Claim Construction Positions

Petitioner argued for the broadest reasonable construction for several key terms, contending these constructions were consistent with the specification and a prior district court ruling.

  • data speculation circuit: Petitioner construed this as "a circuit that detects data dependence between data consuming and data producing instructions and that detects mis-speculation." This construction was asserted to be broad enough to read on the functionality of Hesson’s "writeback unit" and associated logic, which detects "store violation conditions."
  • mis-speculation: Construed as "when a data consuming instruction that is dependent for its data on a data producing instruction appearing earlier in the program order is in fact executed before the data producing instruction." This construction allows for equating the term with Hesson’s "store violation condition," which describes the same event.
  • prediction: Petitioner construed this as "a value that indicates the likelihood that the data speculative execution of a data consuming instruction will result in a mis-speculation." Petitioner argued against a narrower construction from prior litigation that required a prediction to be "capable of receiving ongoing updates," contending that neither the claims nor the specification of the ’752 patent imposes such a limitation. This distinction is critical, as it allows Hesson's "history bits," which are updated based on past events, to qualify as the claimed "prediction."

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-9 of Patent 5,781,752 as unpatentable under 35 U.S.C. §103.