PTAB

IPR2015-00159

Apple Inc v. Memory Integrity LLC A Delaware Ltd Liability Co

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Reducing Probe Traffic In Multiprocessor Systems
  • Brief Description: The ’121 patent discloses techniques for improving data access and cache coherency in multiprocessor systems connected by point-to-point links. The invention focuses on a "probe filtering unit" that receives probes (requests for memory lines) from processing nodes and uses "probe filtering information" to selectively transmit the probes only to the nodes that require them, thereby reducing unnecessary network traffic.

3. Grounds for Unpatentability

Ground 1: Anticipation by Pong - Claims 1-3, 8, 11, 12, 15, 16, and 25 are anticipated by Pong under 35 U.S.C. §102.

  • Prior Art Relied Upon: Pong (Application # 2002/0053004).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Pong, which was not before the examiner during prosecution, discloses every limitation of the challenged independent claims. Pong describes a multiprocessor system with processing nodes interconnected by a point-to-point architecture. Critically, Pong’s "memory controller" performs the exact function of the ’121 patent’s "probe filtering unit." The memory controller receives memory requests (probes), uses a directory that tracks which processors have a copy of a data block (the "probe filtering information"), and leverages this directory to forward the request only to the specific processors known to have the data. The directory’s "presence bit vectors" directly correspond to the claimed "states associated with selected ones of the cache memories."
    • Key Aspects: The core of this argument is that Pong’s memory controller, with its state directory and selective request forwarding, is functionally identical to the "probe filtering unit" that the examiner identified as the patentable feature during the original prosecution.

Ground 2: Obviousness over Pong in view of Gaither - Claim 13 is obvious over Pong and Gaither under 35 U.S.C. §103.

  • Prior Art Relied Upon: Pong (Application # 2002/0053004) and Gaither (Patent 6,662,277).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claim 13 depends from claim 12 and requires a processor to complete a memory transaction after receiving two responses to a probe. Petitioner asserted that Pong teaches completing a transaction after a single response because it describes requesting single memory blocks. Gaither teaches a system that retrieves groups of memory lines with a single request to reduce latency, which can result in multiple responses.
    • Motivation to Combine: A POSITA would combine Pong’s efficient filtering architecture with Gaither’s group-retrieval method to further reduce latency for operations requiring access to contiguous data blocks. This was a known problem with a known solution.
    • Expectation of Success: Combining the references would be straightforward, as both describe multiprocessor cache coherence systems. Implementing Gaither’s group request functionality into Pong’s system would predictably result in a system where a processor receives multiple responses (e.g., two) to a single probe, thus rendering claim 13 obvious.

Ground 3: Obviousness over Pong in view of Duato - Claim 14 is obvious over Pong and Duato under §103.

  • Prior Art Relied Upon: Pong (Application # 2002/0053004) and Duato (a 1997 book, INTERCONNECTION NETWORKS – AN ENGINEERING APPROACH).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claim 14 requires that the probe filtering unit "modify the probes." While Pong discloses the function of forwarding probes, it does not detail the underlying routing mechanism. Duato is a standard textbook describing that routers in an interconnection network function by processing and updating message headers to direct them to their destination.
    • Motivation to Combine: A POSITA implementing Pong’s memory controller (the probe filtering unit) would have been motivated to use a known routing technique, as taught by Duato, to manage the transfer of messages between nodes. Pong’s controller must "address" requests to appropriate processors, and Duato teaches how this is done.
    • Expectation of Success: Implementing a Duato-style router within Pong’s memory controller would inherently require modifying the probe’s header information for proper routing. Therefore, it would have been obvious that the probe filtering unit would be operable to "modify the probes" to perform its function.

Ground 4: Obviousness over Pong in view of Smith - Claims 17-24 are obvious over Pong and Smith under §103.

  • Prior Art Relied Upon: Pong (Application # 2002/0053004) and Smith (a 1997 book, APPLICATION-SPECIFIC INTEGRATED CIRCUITS).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claims 17-24 recite that the probe filtering unit is an integrated circuit, an application-specific integrated circuit (ASIC), or a computer-readable medium with data structures (e.g., a netlist or HDL code) for designing such a circuit. Pong describes the functionality of the memory controller but not its physical implementation. Smith is a standard textbook on ASIC design.
    • Motivation to Combine: Smith teaches that a chip designed to handle the interface between memory and a microprocessor, such as Pong's memory controller, is an ideal candidate for implementation as an ASIC to reduce cost and improve reliability. A POSITA would have been motivated to implement Pong’s controller as an ASIC for these well-known benefits.
    • Expectation of Success: The process of designing an ASIC, as detailed in Smith, directly leads to the creation of the computer-readable media, data structures, code descriptions (HDL), netlists, and semiconductor masks recited in claims 19-24. Thus, the decision to implement Pong's controller as an ASIC would obviously result in the subject matter of these dependent claims.

4. Key Claim Construction Positions

  • "probe filtering information": Petitioner argued this term should be construed broadly as "any criterion that can be used to reduce the number of clusters or nodes probed." This construction is based on the patent’s specification and is broad enough to encompass the "presence bit vectors" used in Pong's directory to track which processors hold a copy of a data block.
  • "transmit the probes only to selected ones of the processing nodes": Petitioner proposed this should be construed as "transmit each of the multiple probes only to one or more selected processing nodes." This construction clarifies that the claim does not require a single probe to be sent to multiple nodes, but that across multiple probe events, the transmissions are directed only to selected nodes, aligning with the functionality described in Pong.

5. Arguments Regarding Discretionary Denial

  • Petitioner disclosed that this petition was being filed concurrently with three other petitions against the same ’121 patent. Petitioner argued that the Board should institute review on all grounds presented across the four petitions to avoid prejudice. It was asserted that the petitions were not redundant, as each one presented distinct grounds necessary to demonstrate the unpatentability of different claims or groups of claims. For example, some grounds relied on prior art that could not be antedated, while others provided the most direct disclosure for specific claim features.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-3, 8, and 11-25 of the ’121 patent as unpatentable based on the grounds presented.