Apple Inc v. Vantage Point Technology Inc

1. Case Identification

• Case #: IPR2015-00191
• Patent #: 5,463,750
• Filed: November 12, 2014
• Petitioner(s): Apple Inc.
• Patent Owner(s): Howard G. Sachs
• Challenged Claims: 8-12

2. Patent Overview

• Title: Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having Multiple Instruction Pipelines and Separate TLB's for Each Pipeline
• Brief Description: The ’750 patent discloses a computing system with multiple instruction pipelines where each pipeline has its own separate Translation Lookaside Buffer (TLB) for virtual address translation services. A central unit handles TLB misses for the multiple pipelines.

3. Grounds for Unpatentability

Ground 1: Obviousness over Titan I and Titan II - Claim 8 is obvious over Titan I in view of Titan II.

• Prior Art Relied Upon: Titan I (a 1991 case study on the Titan supercomputer) and Titan II (a 1988 IEEE article on the Titan architecture).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of Titan I and Titan II, which describe the same Titan graphics supercomputer, teaches every element of independent claim 8. The Titan architecture was described as having a Vector Processing Unit (VPU) with multiple instruction pipelines (e.g., load pipes and a store pipe). These pipelines were associated with separate translation buffers, specifically an R-BUS External TLB (ETLB) for the load pipes and an S-BUS ETLB for the store pipe. Petitioner contended that a single Integer Processing Unit (IPU) in the Titan system functions as the claimed "direct address translation unit," as it services TLB misses for both the R-BUS and S-BUS ETLBs. When a miss occurs, the IPU accesses translation tables (the "master translation memory") stored in main memory to retrieve the correct translation data and load it into the appropriate ETLB.
  • Motivation to Combine: A POSITA would combine Titan I and Titan II because they describe different technical aspects of the same single computer system, the Titan supercomputer. Titan I explicitly cites Titan II, making it natural for a person of ordinary skill to consult both for a complete understanding of the architecture.
  • Expectation of Success: Success was expected because the combination merely involved piecing together disclosed information about a single, existing, and operational system to understand its complete functionality.

Ground 2: Obviousness over Titan I, Titan II, and Hattersley - Claims 9-12 are obvious over Titan I and Titan II in view of Hattersley.

• Prior Art Relied Upon: Titan I, Titan II, and Hattersley (Patent 5,341,485).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground builds on the teachings of Titan I and Titan II and adds Hattersley to address the limitations of dependent claims 9-12, which relate to cross-updating TLBs. Claim 9 requires storing translation data retrieved for a first pipeline's TLB into a second pipeline's TLB. Petitioner asserted that common operations in the Titan architecture (e.g., loading data from memory, performing an operation, and storing the result to the same location) would make such cross-updating desirable to avoid redundant TLB misses. Hattersley explicitly taught this optimization, disclosing a system with multiple TLBs (called DLATs) where a "generated address for one DLAT may be written to all the DLATs" to avoid generating the same address multiple times. This teaching directly corresponds to the cross-updating feature. Claims 11 and 12 add a third pipeline (the IPU's own instruction pipeline) and its associated TLB, which Titan I disclosed as operating in parallel with the VPU pipelines.
  • Motivation to Combine: A POSITA would combine Hattersley with the Titan architecture to improve performance, a primary goal of supercomputing. TLB misses were a known performance bottleneck in the Titan system. Hattersley, which is directed to scientific and vector computing, provided a known solution—cross-updating multiple TLBs—to this exact problem. Applying Hattersley's explicit teaching to the Titan system was therefore a straightforward optimization.
  • Expectation of Success: The combination involved applying a known technique from Hattersley to improve the performance of the known Titan system, leading to the predictable result of reduced TLB misses and increased efficiency.

• Additional Grounds: Petitioner asserted that claim 8 is also obvious over Titan I and Titan II in view of Denning (a 1970 article), which was cited for its explicit teaching of storing translation tables in main memory. A final ground asserted claims 9-12 are obvious over the combination of all four references.

4. Key Claim Construction Positions

• “master translation memory” (claims 8-11): Petitioner argued this term should be construed as the structure in memory that maintains translation data used to reload the translation buffers (TLBs) when a miss occurs. This construction is based on the claim language and context, where the "master" memory provides the complete translation data that is missing from the local TLB caches.
• “a direct address translation unit” (claims 8, 11): Petitioner contended this term requires a single translation unit that is activated to translate virtual addresses from multiple, different pipelines. Petitioner supported this construction by citing a decision in a related IPR (IPR2014-00467) where the Board relied on the claim language (e.g., repeated use of "the direct address translation unit") to conclude a single unit was required, overcoming the general presumption that "a" means "one or more."

5. Arguments Regarding Discretionary Denial

• Petitioner argued that this petition was not redundant with other petitions filed against the ’750 patent. It was distinguished from a concurrently filed petition (IPR2015-00192) by noting that the two petitions presented different prior art grounds and challenged different sets of claims. It was distinguished from a previously filed petition (IPR2015-00175) by asserting that the grounds in the present petition did not rely on infringement contentions from related litigation, whereas the prior petition did, thus presenting a distinct invalidity theory.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 8-12 of Patent 5,463,750 as unpatentable.