LG Electronics Inc v. ATI Technologies ULC

1. Case Identification

• Case #: IPR2015-00321
• Patent #: 7,095,945
• Filed: December 10, 2014
• Petitioner(s): LG Electronics, Inc.
• Patent Owner(s): ATI Technologies ULC
• Challenged Claims: 18 and 21

2. Patent Overview

• Title: Time Shifting of Multiplexed Packetized Data Streams
• Brief Description: The ’945 patent discloses methods and systems for the time-shifting of digital video data. The technology enables a user to record a program, such as from a live broadcast, and play it back from a point of interruption, effectively pausing live television.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 18 and 21 - Claims 18 and 21 are anticipated by Barton under 35 U.S.C. §102(e).

• Prior Art Relied Upon: Barton (Patent 6,233,389).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Barton discloses every limitation of claims 18 and 21. For method claim 18, Petitioner asserted that Barton’s system for multimedia time warping explicitly teaches the three required modes of operation. The first mode (live viewing) is met by Barton’s disclosure of receiving an MPEG stream at a demultiplexer, extracting a program, and decoding it. The second mode (storing) is met by Barton’s disclosure of storing a program in memory. The third mode (simultaneous playback and recording) is met by Barton’s teaching of a second demultiplexer and parser for simultaneous storing and decoding, allowing a user to "store selected television broadcast programs while the user is simultaneously watching or reviewing another program." For system claim 21, Petitioner contended that Barton discloses generating a clock prior to storage, as time stamps are associated with each data segment before being stored in a memory device, and its real-time applications inherently require extracting timing information prior to storage.

Ground 2: Obviousness of Claim 18 - Claim 18 is obvious over Hatanaka in view of O’Connor under 35 U.S.C. §103(a).

• Prior Art Relied Upon: Hatanaka (Patent 6,397,000), O’Connor (Patent 6,591,058).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hatanaka, which discloses a digital signal recording and playback device, teaches most elements of claim 18, including a system with multiple modes of operation for receiving, decoding, and storing broadcast signals. However, should the Board find Hatanaka does not explicitly teach the limitation of "storing a second program portion of the first program simultaneous to the step of decoding," Petitioner contended that O’Connor provides this teaching. O'Connor explicitly describes a time-shifting system that performs "substantially simultaneous recording and playback of the video stream" by alternately storing the incoming stream to a storage unit while reading a different portion from that same unit for playback.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine O’Connor with Hatanaka because both references address the same technical problem in the field of video streaming and time-shifting. A POSITA would have been motivated to incorporate O'Connor's well-understood techniques for simultaneous recording and playback to improve the functionality and user experience of the device disclosed in Hatanaka, particularly to allow users to pause and resume live video without missing content.
  • Expectation of Success: The techniques taught by O'Connor for managing data buffers to achieve simultaneous recording and playback were known methods for improving video streaming devices. Therefore, a POSITA would have had a reasonable expectation of success in applying these established principles to the Hatanaka system.

Ground 3: Obviousness of Claim 21 - Claim 21 is obvious over Fujinami under 35 U.S.C. §103(a).

• Prior Art Relied Upon: Fujinami (Patent 5,521,922).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Fujinami discloses all elements of system claim 21. Fujinami describes a data demultiplexer for processing time-division multiplex data from an optical disk. It discloses receiving packetized data, separating it into video, audio, and timing data (such as System Clock Reference, SCR, and Decoding Time Stamp, DTS), and storing the video/audio data in code buffers. Crucially, Fujinami discloses a "system time clock generation means" that generates a clock based on the received SCR timing information. This clock is generated before the selected video/audio packets are fully processed for decoding, thereby meeting the limitation that a clock is generated based on received timing information "before the select packets are stored in the storage device."
  • Motivation to Combine: This argument is based on a single reference. Petitioner asserted it would have been obvious to a POSITA to use the stored timing information (SCR and DTS) explicitly disclosed by Fujinami for its intended and conventional purpose: generating a clock signal at the output to ensure synchronized decoding and playback of the buffered video and audio data.
  • Expectation of Success: Using timing information embedded in a multiplexed stream to generate a system clock for synchronized playback was a fundamental and predictable technique in digital video systems at the time. A POSITA would have readily understood how to implement this function with a high expectation of success.
• Additional Grounds: Petitioner asserted additional challenges, including that claim 18 is obvious over Hatanaka alone and that claim 21 is anticipated by Hatanaka.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 18 and 21 of the ’945 patent as unpatentable.