PTAB

IPR2015-00327

LG Electronics Inc v. ATI Technologies Inc

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1. Case Identification

2. Patent Overview

  • Title: Graphics Processor with Unified Shader
  • Brief Description: The ’871 patent describes a graphics processing architecture that uses a single, unified shader to perform both vertex and pixel operations. This contrasts with conventional architectures that use separate, dedicated shaders for each type of operation.

3. Grounds for Unpatentability

Ground 1: Anticipation over Stuttard - Claims 1-2, 5, 13, and 15 are anticipated by Stuttard.

  • Prior Art Relied Upon: Stuttard (Patent 7,363,472).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Stuttard, which describes a graphics processing system using multithreading, discloses every element of the challenged claims. Stuttard’s “processing core 10” and its associated processing elements (PEs) function as the claimed unified “shader” because they are disclosed to perform both vertex (geometry) processing and subsequent pixel processing. The “thread manager 102” in Stuttard acts as the claimed “arbiter circuit” by controlling the transfer of data and instructions to the processing core for either vertex or pixel operations. For dependent claims, Stuttard’s local memory serves as the “vertex storage block” (claim 2), its PE register file is the “register block” (claims 13, 15), its processor unit is the “computation element” (claim 13), and its instruction sequencer is the “sequencer” (claims 13, 15).

Ground 2: Obviousness over Stuttard and OpenGL - Claims 3, 6, 8, 10, and 11 are obvious over Stuttard in view of OpenGL.

  • Prior Art Relied Upon: Stuttard (Patent 7,363,472) and OpenGL (OpenGL Graphics System: A Specification, Version 1.4).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Stuttard’s unified shader architecture provides the base system. OpenGL, a widely used graphics API specification, was asserted to supply the missing elements for the dependent claims. For claim 3, while Stuttard discloses a "vertex storage block" (local memory), it does not explicitly detail separate parameter and position caches. OpenGL teaches that vertex processing separates vertex information into position data (coordinates) and appearance attribute data (parameters like color). For claim 10, Stuttard's processing core performs the function of primitive assembly, but OpenGL explicitly teaches using a distinct "primitive assembly block" in the graphics pipeline.
    • Motivation to Combine: A POSITA would combine the teachings of Stuttard and OpenGL because both relate to 3D graphics processing, and OpenGL was a well-known standard. A POSITA would modify Stuttard’s memory system to include separate position and parameter caches as taught by OpenGL to achieve faster access to processed vertex data. Similarly, a POSITA would be motivated to implement a dedicated primitive assembly block as taught by OpenGL to simplify the architecture of Stuttard’s processing core and separate distinct functions.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in making these combinations, as they involved applying a standard graphics pipeline structure (from OpenGL) to a known processor architecture (Stuttard) to achieve predictable benefits in performance and design simplicity.

Ground 3: Anticipation over Owens - Claims 1-2, 5-6, 8, 13, 15, and 17 are anticipated by Owens.

  • Prior Art Relied Upon: Owens (“Polygon Rendering on a Stream Architecture”).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Owens, which describes a polygon rendering system on a programmable stream processor, discloses all limitations of the claims. Owens’s system uses the same hardware (ALU clusters) to perform both vertex and pixel operations, corresponding to the claimed unified “shader.” The “stream controller” in Owens, which sequences and issues stream operations to the ALU clusters, functions as the claimed “arbiter circuit.” The pipeline in Owens is explicitly described as OpenGL-like, processing geometry (position), color, and depth attributes, thereby disclosing the limitations of claims 5, 6, and 8. Owens’s Stream Register File (SRF) serves as the “vertex storage block” (claim 2), and its microcontroller, which stores instructions and controls kernel execution in the ALU clusters, serves as the “sequencer” (claims 13, 15).

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations including Stuttard with Kizhepat (Patent 7,376,811) and Kurihara (Patent 5,500,939), as well as Owens with OpenGL, Kizhepat, and Kurihara, relying on similar theories for adding known graphics processing components to improve performance or simplify design.

4. Key Claim Construction Positions

  • “Includes”/“Including”: Petitioner argued this term should be construed to mean “contains or connected to.” This construction was based on the ’871 patent’s specification, which describes a multiplexer (a selection circuit) as being connected to the unified shader, not necessarily contained within it. This broader interpretation is critical for mapping prior art where control or selection circuits are external but coupled to the main processing unit.
  • “Means for performing vertex operations and pixel operations” (Claim 1): Petitioner proposed this means-plus-function limitation should be construed according to §112, ¶ 6. The claimed function is “performing vertex operations and pixel operations,” and the corresponding structure disclosed in the ’871 patent’s specification is the unified shader’s processor (CPU 96) and its equivalents.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-6, 8-11, 13, 15, 17-18, and 20 of the ’871 patent as unpatentable.