PTAB
IPR2015-00592
MaxLinear Inc v. Cresta Technology Corp
Key Events
Petition
Table of Contents
petition
1. Case Identification
- Case #: IPR2015-00592
- Patent #: 7,075,585
- Filed: January 28, 2015
- Petitioner(s): MaxLinear, Inc.
- Patent Owner(s): Cresta Technology Corporation
- Challenged Claims: 1-21
2. Patent Overview
- Title: Broadband Receiver having a Multistandard Channel Filter
- Brief Description: The ’585 patent discloses a television receiver capable of processing signals from multiple standards and formats (e.g., analog, digital). The invention purports to improve on prior art by digitizing the intermediate frequency (IF) signal and performing channel filtering using a programmable digital signal processor (DSP).
3. Grounds for Unpatentability
Ground 1: Claims 1, 2, 4, 5, 10, and 12-20 are obvious over VDP in view of Ishikawa.
- Prior Art Relied Upon: VDP (Patent 6,643,502) and Ishikawa (Patent 5,418,815).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that VDP, a primary reference from the patent’s prosecution, taught a multi-standard receiver that processed an IF signal in the digital domain, meeting most limitations of independent claims 1 and 17. However, the claims were allowed over VDP based on the limitation of a "plurality of demodulators." Petitioner asserted that this feature was well-known and explicitly taught by Ishikawa, which discloses a receiver architecture using separate, parallel demodulators for analog and digital signal formats. The combination of VDP’s core architecture with Ishikawa’s modular demodulator system was alleged to render the independent claims obvious.
- Motivation to Combine: A POSITA would combine VDP and Ishikawa as both address multi-standard, multi-format television receivers with digital-IF architectures. Petitioner argued a POSITA would be motivated to replace VDP’s single, combined demodulator with Ishikawa’s system of separate demodulators to add flexibility, allowing for the independent optimization of demodulation for different signal formats.
- Expectation of Success: A POSITA would have an expectation of success because Ishikawa's modular design enables the straightforward parallel addition of demodulators to a system like VDP's without altering its fundamental operation or requiring undue experimentation.
Ground 2: Claim 3 is obvious over VDP in view of Ishikawa and Malkemes.
- Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Malkemes (WO 01/20792).
- Core Argument for this Ground:
- Prior Art Mapping: Claim 3 adds a digital-to-analog converter (DAC) coupled between the signal processor and one of the demodulators. Petitioner contended that while the VDP/Ishikawa combination supplied the base multi-demodulator receiver, Malkemes taught the specific implementation of using a DAC to convert a digitally processed IF signal back to an analog signal before it is fed to an analog demodulator.
- Motivation to Combine: Malkemes teaches a multi-standard TV receiver and demonstrates using a DAC to interface a digital front-end with subsequent analog processing blocks. A POSITA would be motivated to incorporate the DAC taught by Malkemes into the VDP/Ishikawa architecture to enable the use of a well-known analog demodulator, a predictable design choice for handling analog formats.
Ground 3: Claims 6, 7, 9, and 21 are obvious over VDP in view of Ishikawa and Balaban.
- Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Balaban (Patent 6,369,857).
- Core Argument for this Ground:
- Prior Art Mapping: These dependent claims add limitations regarding filter and sampling frequencies being functions of the IF (claims 6, 21), a tuning control circuit (claim 7), and a 10-bit analog-to-digital converter (ADC) (claim 9). Petitioner argued that Balaban, which discloses a receiver for both analog and digital television, taught these specific features. Balaban explicitly described selecting the ADC sampling frequency based on the IF to avoid aliasing, using a control circuit to adjust these frequencies, and specified that a 10-bit ADC was typical for such applications.
- Motivation to Combine: A POSITA would incorporate the teachings of Balaban into the primary VDP/Ishikawa combination to implement standard, well-known techniques for improving receiver performance. Optimizing sampling rates and ADC resolution as taught by Balaban was a predictable path to enhancing reception quality.
- Additional Grounds: Petitioner asserted additional obviousness challenges for claim 8 over VDP, Ishikawa, and Tsividis (teaching a transconductance filter for anti-aliasing) and for claim 11 over VDP, Ishikawa, and Greenberg (teaching storing filter coefficients in a memory indexed by a signal processor).
4. Key Claim Construction Positions
- "format": Petitioner proposed construing "format" as a "distinct signal format, such as analog or digital." This construction was central to its argument that Ishikawa’s teaching of separate demodulators for analog and digital formats directly corresponded to the patent’s requirement for demodulators that operate according to one of a "plurality of formats."
- "video and audio baseband signals": Petitioner proposed construing this term as "at least one signal without transmission modulation." This broad construction was argued to be necessary because a demodulator for a digital format outputs a single data stream (e.g., MPEG), not separate video and audio signals as an analog demodulator would.
5. Arguments Regarding Discretionary Denial
- Petitioner argued that the grounds presented were not redundant of prior proceedings. It contended the challenge was superior to the original prosecution because the Examiner did not consider Ishikawa, which allegedly supplied the key missing element (plurality of demodulators) that led to the patent's allowance. Petitioner also distinguished its grounds from those in co-pending IPRs (IPR2014-00728 and IPR2015-00615) by asserting its reliance on VDP and Ishikawa was stronger and addressed claims not included in those other petitions.
6. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 1-21 of Patent 7,075,585 as unpatentable.
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