PTAB

IPR2015-00592

MaxLinear, Inc. v. Cresta Technology Corporation

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1. Case Identification

2. Patent Overview

  • Title: Broadband Receiver having a Multistandard Channel Filter
  • Brief Description: The ’585 patent discloses a broadband television receiver designed to process signals from multiple broadcast standards and formats. The invention purports to solve shortcomings of prior art systems by replacing a bank of analog channel filters with a programmable digital channel filter architecture that processes an intermediate frequency (IF) signal in the digital domain.

3. Grounds for Unpatentability

Ground 1: Obviousness over VDP and Ishikawa - Claims 1, 2, 4, 5, 10, and 12-20 are obvious over VDP in view of Ishikawa.

  • Prior Art Relied Upon: VDP (Patent 6,643,502) and Ishikawa (Patent 5,418,815).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that VDP, which was considered during original prosecution, discloses a multi-standard receiver architecture with a digital-IF that meets nearly all limitations of independent claims 1 and 17. However, the Examiner allowed the claims based on the "plurality of demodulators" limitation, which VDP allegedly lacked. Petitioner asserted that Ishikawa, which was not before the Examiner, explicitly teaches a multi-standard receiver that uses a plurality of separate demodulators for different formats (analog and digital).
    • Motivation to Combine: Petitioner contended that both VDP and Ishikawa disclose multi-standard, multi-format television receivers that perform channel filtering in the digital domain. A person of ordinary skill in the art (POSITA) would combine Ishikawa’s modular system concept, with its separate demodulators, into VDP’s architecture to gain the flexibility of adding or removing hardware elements for different formats while maintaining system integrity.
    • Expectation of Success: A POSITA would have a high expectation of success because both references operate in the same technical field, address the same problems, and use compatible digital-IF architectures. The combination represents integrating a known modular demodulation scheme into a known receiver front-end.

Ground 2: Obviousness over VDP, Ishikawa, and Malkemes - Claim 3 is obvious over VDP in view of Ishikawa and further in view of Malkemes.

  • Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Malkemes (WO 01/20792).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 to address dependent claim 3, which adds a digital-to-analog converter (DAC) coupled between the signal processor and one of the demodulators. Petitioner argued that Malkemes explicitly teaches a multi-standard receiver where a DAC is used to convert the digitally processed IF signal back to an analog format to interface with an analog demodulator.
    • Motivation to Combine: A POSITA, having combined VDP and Ishikawa, would look to a reference like Malkemes to solve the problem of interfacing the digital signal processor with an analog demodulator. Incorporating a DAC as taught by Malkemes was a known and predictable solution for achieving interoperability between digital and analog components.

Ground 3: Obviousness over VDP, Ishikawa, and Balaban - Claims 6, 7, 9, and 21 are obvious over VDP in view of Ishikawa and further in view of Balaban.

  • Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Balaban (Patent 6,369,857).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targeted claims related to the analog-to-digital converter (ADC) and its control. Petitioner asserted that Balaban teaches making the anti-aliasing filter's center frequency and the ADC's sampling frequency functions of the intermediate frequency (claim 6), using a tuning control circuit for adjustment (claim 7), and using a 10-bit ADC for improved resolution (claim 9).
    • Motivation to Combine: A POSITA would incorporate Balaban's teachings to improve receiver performance. Using a higher-resolution ADC and dynamically adjusting filter and sampling parameters to avoid aliasing are well-known techniques for optimizing multi-standard receivers.

Ground 4: Obviousness over VDP, Ishikawa, and Tsividis - Claim 8 is obvious over VDP in view of Ishikawa and further in view of Tsividis.

  • Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Tsividis (IEEE Journal of Solid-State Circuits, Mar. 1994).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targeted dependent claim 8, which requires the anti-aliasing filter to comprise a transconductance (gmC) filter function. Petitioner argued that Tsividis is a well-known reference on integrated filter design that explicitly discloses using gmC filters for anti-aliasing purposes in television receivers.
    • Motivation to Combine: A POSITA designing an integrated circuit receiver would naturally consult a foundational text like Tsividis to select a suitable filter. The use of a gmC filter was an obvious and common design choice for implementing a compact and efficient on-chip anti-aliasing filter.

Ground 5: Obviousness over VDP, Ishikawa, and Greenberg - Claim 11 is obvious over VDP in view of Ishikawa and further in view of Greenberg.

  • Prior Art Relied Upon: VDP (Patent 6,643,502), Ishikawa (Patent 5,418,815), and Greenberg (Patent 5,278,872).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claim 11, which recites storing finite impulse response (FIR) filters in a memory and indexing that memory to retrieve them. Petitioner argued that Greenberg teaches a television receiver architecture where a DSP with memory stores and periodically reloads FIR filter coefficients.
    • Motivation to Combine: A POSITA would incorporate Greenberg’s programmable filter architecture to add the flexibility of reloading filter coefficients without changing hardware. This is a clear and obvious advantage for a multi-standard receiver that must adapt its filtering characteristics based on the received signal's format.

4. Key Claim Construction Positions

  • "format": Petitioner proposed construing this term as a "distinct signal format, such as analog or digital." This construction was argued as crucial to distinguish between signal formats and television "standards" (e.g., NTSC, PAL), thereby supporting the argument that Ishikawa's separate demodulators for analog and digital formats were directly relevant.
  • "video and audio baseband signals" / "baseband signals": Petitioner proposed construing these plural terms as "at least one signal without transmission modulation." This broad construction was argued to be necessary to encompass digital formats, which may output a single data stream (e.g., MPEG) rather than separate video and audio signals, thus preventing the claims from being improperly limited to only analog formats.
  • "signal processor": Petitioner proposed this term means a "digital module that processes signals in the digital domain," clarifying the scope of the invention's core processing unit.

5. Arguments Regarding Discretionary Denial

  • Non-Redundancy with Prosecution: Petitioner argued that the grounds presented were not redundant of arguments made during original prosecution. The central argument was that the primary combination relied on Ishikawa, which was not before the Examiner. Petitioner asserted that Ishikawa directly teaches the "plurality of demodulators" limitation that the Examiner had considered novel and was the basis for allowing the claims.
  • Non-Redundancy with Other IPRs: Petitioner also argued that its grounds were not redundant of two related IPRs filed by Silicon Labs (IPR2014-00728 and IPR2015-00615). Those petitions relied on a different primary reference (Thomson). Petitioner contended that its chosen primary reference, VDP, was stronger prior art because it was the same reference relied upon by the Examiner and its terminology more closely matched that of the challenged patent.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-21 of the ’585 patent as unpatentable.