ATopTech Inc v. Synopsys Inc

1. Case Identification

• Case #: IPR2015-00760
• Patent #: 6,237,127
• Filed: February 18, 2015
• Petitioner(s): ATopTech, Inc.
• Patent Owner(s): Synopsys, Inc.
• Challenged Claims: 5-6

2. Patent Overview

• Title: Static Timing Analysis with Exceptions
• Brief Description: The ’127 patent describes a method for performing static timing analysis on an electronic circuit design. The method involves propagating timing data through a circuit description and using "exceptions"—user-defined, non-default timing constraints—to manage and verify specific signal paths, such as false paths that are not logically realizable.

3. Grounds for Unpatentability

Ground 1: Obviousness over Belkhale - Claims 5-6 are obvious over Belkhale.

• Prior Art Relied Upon: Belkhale ("Timing Analysis with known False Sub Graphs," 1995 IEEE/ACM International Conference of Computer-Aided Design – Digest of Technical Papers).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Belkhale taught every limitation of claims 5 and 6. Belkhale described a static timing analysis method that identified and removed "false sub graphs," which Petitioner asserted were analogous to the ’127 patent’s "exceptions." Belkhale propagated timing values (Arrival Times, or ATs) through a circuit graph. To track the exceptions, Belkhale attached a "set attribute" to each timing value, which identified the set of false sub graphs a signal had passed through. Petitioner contended this "set attribute" was the claimed "tag comprising at least a first label." Belkhale’s algorithm satisfied the exception by checking if a propagated path had fully traversed a false sub graph. This check occurred during the calculation of timing values and prior to the final comparison against a constraint value (slack calculation), thus meeting a key limitation of claim 5. For claim 6, Belkhale modified the constraint value (Required Arrival Time, or RAT) to "NO RAT" for paths determined to be false, which Petitioner argued was equivalent to "modifying the first constraint value...according to the satisfied exception."
  • Expectation of Success: As Belkhale described a complete, working algorithm for timing analysis that incorporated the management of false paths, a POSITA would have had a high expectation of successfully implementing its teachings.

Ground 2: Obviousness over Belkhale in view of Tom - Claims 5-6 are obvious over Belkhale in view of Tom.

• Prior Art Relied Upon: Belkhale and Tom (Patent 5,210,700).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative, particularly if the claims were construed to require a "tag" that identifies a clock and a "timing table" with multiple delay values. Belkhale provided the fundamental method for handling exceptions (false paths) using a tag-like "set attribute." Tom taught a static timing analysis method that used "clock tags" to associate specific clocking information with propagated delay values. Tom also explicitly taught propagating multiple delay values (e.g., for logical high and low signals) within its timing tables. The combination of Belkhale's exception handling with Tom's clock tagging and multi-value timing tables would render the claims obvious.
  • Motivation to Combine: A POSITA would combine these references to create a more comprehensive and accurate static timing analysis system. Both references addressed modifying default timing analysis using tags to track additional information. A POSITA seeking to apply Belkhale’s advanced false path analysis to a realistic, complex circuit with multiple clock domains (as addressed by Tom) would have found it obvious to incorporate Tom's clock-specific tags into Belkhale’s existing tag structure. This would allow the system to handle both false path exceptions and multi-cycle clocking adjustments simultaneously, leading to a more robust and less error-prone analysis.
  • Expectation of Success: The combination involved applying known tagging techniques from one timing analysis system to another to track an additional, known type of circuit information. A POSITA would have reasonably expected success in integrating these similar and complementary methods.

4. Key Claim Construction Positions

• Adoption of Board’s Prior Construction: This petition was filed after a prior IPR on the same patent (IPR2014-001145) where the Board did not institute trial on claims 5 and 6 because it adopted a claim construction different from the one Petitioner proposed. For this petition, Petitioner expressly adopted the Board's construction of claim 5—specifically that the claim recites "satisfying an exception ... with the first label" rather than comparing a timing value with a label—to demonstrate that the claims were obvious even under the Board's own interpretation.
• "Exception": Petitioner argued this term should be construed as "a non-default timing constraint," a construction the Board had previously adopted.
• "Tag": Petitioner contended that the plain language of claim 1 required only "a tag comprising at least a first label," not a second label identifying a clock, and proposed the construction "a data structure comprising at least one label."

5. Arguments Regarding Discretionary Denial

• Petitioner's arguments implicitly countered potential discretionary denial under 35 U.S.C. § 325(d). The petition explained that claims 5 and 6 were not instituted in a prior IPR because the Board adopted a different claim construction than what Petitioner had argued. This petition was specifically tailored to prove the claims unpatentable under the Board’s own construction from that prior proceeding. This presented a new, material argument not previously considered, addressing the precise reason for the prior non-institution and justifying a new review. The petition was also accompanied by a motion for joinder with the earlier IPR.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 5 and 6 of Patent 6,237,127 as unpatentable.