Apple Inc v. ZiiLabs Inc

1. Case Identification

• Case #: IPR2015-00930
• Patent #: 8,144,156
• Filed: March 27, 2015
• Petitioner(s): Apple Inc.
• Patent Owner(s): ZIILABS INC., LTD.
• Challenged Claims: 6, 9, 11, and 14

2. Patent Overview

• Title: Sequencer with Async SIMD Array
• Brief Description: The ’156 patent discloses a multi-threaded graphics processing architecture designed to improve efficiency. The core concept involves placing a buffer between a sequencer and an array of processing elements (PEs) to decouple their operations, allowing the PEs to continue processing data even if the sequencer stalls.

3. Grounds for Unpatentability

Ground 1: Obviousness over Miyaguchi and Stuttard - Claims 6, 9, 11, and 14 are obvious over Miyaguchi in view of Stuttard.

• Prior Art Relied Upon: Miyaguchi (Patent 6,763,450) and Stuttard (WO 00/62182).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Miyaguchi taught the core architecture of the challenged claims, including a parallel rendering architecture with a sequencer (instruction generator), a plurality of SIMD processing elements, and a FIFO buffer placed between them. This buffer decouples the sequencer and processing elements, allowing them to operate asynchronously and at different rates, thereby satisfying many limitations of independent claims 6 and 11. However, Petitioner contended Miyaguchi did not explicitly teach automatically transferring processing to a new set of data items specifically upon a stall.
  • Motivation to Combine: Petitioner asserted Stuttard supplied the missing element. Stuttard described a graphics data processing system with a thread manager that automatically transfers processing to another thread when the current one is "halted" to keep the processing element array active. A person of ordinary skill in the art (POSITA) would combine Miyaguchi and Stuttard because both references address improving efficiency in graphics/video processors using similar parallel SIMD architectures and FIFO buffers. A POSITA would have been motivated to incorporate Stuttard's well-known stall-handling technique into Miyaguchi’s similar architecture to further improve performance.
  • Expectation of Success: Given that digital circuit design was a highly predictable field, a POSITA would have had a high expectation of success in integrating Stuttard’s automatic process transfer capability into the Miyaguchi architecture as a routine design modification.

Ground 2: Obviousness over Miyaguchi and Moy - Claims 6, 9, 11, and 14 are obvious over Miyaguchi in view of Moy.

• Prior Art Relied Upon: Miyaguchi (Patent 6,763,450) and Moy (Patent 7,310,722).
• Core Argument for this Ground:
  • Prior Art Mapping: Similar to the first ground, Petitioner relied on Miyaguchi for the foundational architecture of a sequencer, SIMD PEs, and a decoupling buffer. The combination with Moy was argued to render the claims obvious by teaching the automatic transfer of processing upon a stall and explicitly applying the architecture to 3D graphics. Moy disclosed a dispatch circuit in a graphics processor that, upon encountering a blocked or "stalled" thread, automatically issues ready instructions from other threads to avoid pipeline "bubbles."
  • Motivation to Combine: A POSITA would combine these references as they both seek to solve the same problem of processing inefficiency in parallel graphics systems. Moy explicitly taught adapting such architectures for 3D graphics and provided a specific solution for reducing stalls. Petitioner argued it would have been obvious to apply Moy's stall-mitigation technique to Miyaguchi's architecture to improve its performance, especially when adapting it for the 3D graphics applications suggested by Moy.
  • Expectation of Success: Petitioner argued a POSITA would have readily incorporated Moy's automatic transfer technique into the Miyaguchi architecture with a high expectation of success, viewing it as an obvious way to enhance a known processor design.

4. Key Claim Construction Positions

• "Asynchronous" / "Decouples operations": Petitioner argued for constructions centered on the concept of not running in "lock step." For example, "asynchronous" was proposed as "not having to run in lock step." This construction was asserted to be consistent with the ’156 patent’s disclosure that a buffer between the sequencer and PEs allows them to be decoupled.
• "Automatically transfers processing": Petitioner proposed this term be construed as "transfers... processing without receiving an instruction." This construction was based on the specification's description of a sequencer switching threads upon detecting a potential stall. Petitioner argued this construction was critical to distinguish from systems that require an explicit "yield instruction," a concept Petitioner contended was absent from the patent's disclosure but potentially argued by the Patent Owner in concurrent litigation.
• "Sequencer": Petitioner proposed construing this term as a "unit that controls instruction flow and calculates the address of and fetches the next instruction." This construction was based on descriptions of conventional sequencers in the patent's background and prosecution history, and it was argued to be broader than a potential construction that also included decoding commands, a function already recited separately in the claims.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 6, 9, 11, and 14 of the ’156 patent as unpatentable.