SanDisk Corp v. Netlist Inc

1. Case Identification

• Case #: IPR2015-01020
• Patent #: 7,881,150
• Filed: April 7, 2015
• Petitioner(s): SanDisk Corporation
• Patent Owner(s): Netlist, Inc.
• Challenged Claims: 15-17, 22, 24, 26, 31-33

2. Patent Overview

• Title: Memory Module with a Circuit for Translating Between System and Physical Memory Domains
• Brief Description: The ’150 patent discloses a memory module with a circuit that allows a computer system to interface with more memory devices (e.g., in more ranks) than its memory controller is designed to support. The circuit translates signals between the system's expected memory configuration and the module's actual, higher-density physical memory configuration.

3. Grounds for Unpatentability

Ground 1: Obviousness over Takeda and JEDEC - Claims 15, 16, 31, and 32 are obvious over Takeda in view of JEDEC.

• Prior Art Relied Upon: Takeda (Japanese Patent Publication No. H10-320270) and JEDEC (JEDEC Standard 21-C: DDR SDRAM Registered DIMM Design Specification).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Takeda disclosed the core inventive concept: a memory module with more memory banks (ranks) than expected by the host computer system. Takeda’s "bank control unit" receives a first number of chip-select signals and address signals and translates them into a second, greater number of chip-select signals to control the additional ranks. This directly maps to the claimed translation between a "system memory domain" and a "physical memory domain." Petitioner contended that while Takeda did not explicitly show a register or a phase-lock loop (PLL), the JEDEC standard, which a person of ordinary skill in the art (POSITA) would consult for implementing a DDR memory module, explicitly discloses these components as standard parts of a registered DIMM architecture. JEDEC provides the standard signals, data lines, and component layouts for a DDR memory module, filling in the conventional architectural details for Takeda’s system.
  • Motivation to Combine: A POSITA implementing Takeda's rank-multiplication concept for a modern DDR system would have been motivated to consult and apply the industry-standard JEDEC specification. Takeda itself mentions that memory module configurations are disclosed in JEDEC documents. The motivation was to apply Takeda's known technique to the well-defined DDR architecture in JEDEC to achieve the predictable benefits of increased memory capacity using lower-cost, lower-density memory chips.
  • Expectation of Success: Success was expected because the combination merely involved applying Takeda's known logic for rank multiplication to the standard, predictable, and well-documented DDR memory architecture defined by JEDEC.

Ground 2: Obviousness over Takeda, JEDEC, and Connolly - Claims 17, 22, 24, 26, and 33 are obvious over Takeda and JEDEC, further in view of Connolly.

• Prior Art Relied Upon: Takeda (Japanese Patent Publication No. H10-320270), JEDEC (JEDEC Standard 21-C), and Connolly (Patent 6,070,217).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the Takeda/JEDEC combination to address limitations related to selective electrical isolation and switches, which are recited in independent claim 22 and various dependent claims. Petitioner asserted that Connolly taught the missing element: using "in-line bus switches" on a memory module to selectively isolate the capacitive load of memory devices from the computer system's data bus. This technique was used to minimize bus loading, a known problem in high-density memory modules. Petitioner mapped Connolly’s disclosure of using switches to selectively couple/decouple memory devices from the data bus directly onto the "selectively isolating one or more loads" limitation of claim 22 and the "one or more switches" limitation of dependent claims 17 and 33.
  • Motivation to Combine: A POSITA designing a high-density memory module based on Takeda and JEDEC would have confronted the known problem of increased capacitive bus loading. Petitioner argued this POSITA would combine Connolly's well-known solution for reducing this load to improve the overall performance and power consumption of the module. All three references address the common goal of creating higher-density memory modules for computer systems.
  • Expectation of Success: A POSITA would have had a high expectation of success, as combining Connolly's load-isolation switches with a standard memory module design was a known technique for achieving the predictable benefit of reduced bus capacitance.

Ground 3: Anticipation by Amidi - Claims 15 and 31 are anticipated by Amidi.

• Prior Art Relied Upon: Amidi (Application # 2006/0117152).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner contended that Amidi disclosed every element of independent claims 15 and 31. Amidi describes a "transparent four rank DDR module" designed to emulate a two-rank module for a computer system. The module explicitly includes all claimed components mounted together: DDR memory devices arranged in ranks, a register, a phase-lock loop (PLL), and a complex programmable logic device (CPLD) that serves as the claimed "logic element." Amidi's CPLD performs the exact function recited in the claims: it receives a first number of chip-select signals (e.g., two) from the computer and translates them into a second, greater number of chip-select signals (e.g., four) to manage the physical ranks. Amidi also discloses the claimed motivation of using more lower-density memory devices to reduce cost, thus teaching the translation between a higher-density system domain and a lower-density physical domain.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 16 and 32 are obvious over Amidi alone, and that claims 17, 22, 24, 26, and 33 are obvious over Amidi in view of Connolly, relying on similar load-isolation theories as presented in Ground 2.

4. Key Claim Construction Positions

• "operationally coupled to": Petitioner argued that this term, which appears in all independent claims to describe the relationship between the PLL and other module components, should be construed as "functionally cooperating with." The basis for this construction was that in the context of the ’150 patent’s disclosure, the PLL, memory devices, register, and logic element are all shown as components on a single printed circuit board that must work together to perform memory operations. Petitioner noted that the Patent Owner had previously agreed to this construction in related district court litigation.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 15-17, 22, 24, 26, and 31-33 of Patent 7,881,150 as unpatentable.