NVIDIA Corp v. Samsung Electronics Co Ltd

1. Case Identification

• Case #: IPR2015-01062
• Patent #: 7,056,776
• Filed: April 17, 2015
• Petitioner(s): NVIDIA Corp.
• Patent Owner(s): Samsung Electronics Co., Ltd.
• Challenged Claims: 1, 2, 4, 19, 20, and 22

2. Patent Overview

• Title: Semiconductor Devices Having Metal Containing N-type and P-type Gate Electrodes and Methods of Forming the Same
• Brief Description: The ’776 patent discloses methods for fabricating complementary metal-oxide-semiconductor (CMOS) devices with distinct N-type and P-type gate electrodes. The invention focuses on creating metal-containing gate electrodes with different work functions to achieve improved transistor performance, such as surface channel operation and reduced threshold voltages.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 1, 2, 4, 19, 20, and 22 are anticipated under 35 U.S.C. §102(e) by the ’950 patent.

• Prior Art Relied Upon: Adke (Patent 7,316,950), hereafter "’950 patent".
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the ’950 patent, which was not considered during the prosecution of the ’776 patent, discloses every element of the challenged claims. For independent claim 1, Petitioner asserted the ’950 patent teaches a CMOS device with two different gate electrodes: a first (NMOS) gate electrode comprising a lower NMOS metal pattern and an upper PMOS metal pattern, and a second (PMOS) gate electrode comprising a single PMOS metal pattern. The ’950 patent allegedly discloses that the first and third metal patterns (the NMOS and PMOS patterns adjacent to the insulation layer, respectively) have different work functions (4.4 eV and 4.9 eV). Petitioner contended that figures in the ’950 patent show the top surfaces of the second and third metal-containing patterns are substantially planar as they are formed from a single planarized layer of deposited PMOS metal. The arguments for method claim 19 were presented as parallel to those for device claim 1, with dependent claims 2, 4, 20, and 22 being met by disclosures that the gate insulation layers comprise the same material (SiO2) and have the same thickness.

Ground 2: Obviousness - Claims 1, 2, 4, 19, 20, and 22 are obvious over the ’950 patent in view of the ’695 patent.

• Prior Art Relied Upon: ’950 patent and Xiang (Patent 6,838,695), hereafter "’695 patent".
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that, to the extent the ’950 patent is found not to explicitly teach that the top surfaces of the gate electrodes are substantially planar, this feature would have been obvious to a person of ordinary skill in the art (POSITA) in view of the ’695 patent. The ’950 patent provided the base method of forming dual metal gate electrodes. The ’695 patent was cited for its teaching of using a chemical mechanical polishing (CMP) process to planarize a deposited gate electrode layer (polysilicon) to eliminate topography before the gate patterning step. This planarization results in gate electrodes with planar top surfaces.
  • Motivation to Combine: A POSITA would combine these references because both are directed to "gate-first" fabrication of CMOS devices and address the common problem of non-planar topography that arises when depositing a top gate electrode layer over a patterned underlying layer. Petitioner asserted it was well-known that non-planar surfaces degrade subsequent photolithography steps and can cause damage to the substrate during etching. The ’695 patent provided a known solution (CMP) to this known problem. The fact that ’695 used polysilicon while ’950 used metal was argued to be immaterial to the mechanical problem of non-planarity.
  • Expectation of Success: A POSITA would have had a high expectation of success, as CMP was a conventional, predictable, and widely used technique for planarizing surfaces in semiconductor manufacturing to improve device yield and reliability.

4. Key Claim Construction Positions

• "gate electrode": Petitioner proposed this term be construed as "a conductive structure distinct from any low-resistance conductive pattern, which controls the flow of current through the channel of a transistor." This construction was based on the ’776 patent’s consistent distinction between "gate electrodes" and separate, "stacked on" structures referred to as "low-resistance conductive patterns."
• "substantially planar": For the phrase "the third metal-containing conductive pattern has a surface... that is substantially planar with the surface of the second metal-containing conductive pattern," Petitioner proposed a construction tied to the function disclosed in the specification: "the surfaces... are sufficiently equivalent in height so as to prevent damage to the substrate during the etch process forming the gate electrodes."
• "different work functions": Petitioner argued this phrase should be construed as "the work function of the first metal-containing conductive pattern at its bottom surface is different from the work function of the third metal-containing conductive pattern at its bottom surface." This was based on the technical principle that only the work function at the interface with the gate insulation layer affects the transistor's channel behavior and threshold voltage.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and cancellation of claims 1, 2, 4, 19, 20, and 22 of the ’776 patent as unpatentable.