Dell Inc v. NXP BV

1. Case Identification

• Case #: IPR2015-01082
• Patent #: 6,590,365
• Filed: April 21, 2015
• Petitioner(s): Dell Inc.
• Patent Owner(s): NXP BV.
• Challenged Claims: 1, 2, 4, 5, 7, 9, 15-17

2. Patent Overview

• Title: Method of Powering-Up Battery Powered Apparatus
• Brief Description: The ’365 patent discloses methods and equipment for powering up battery-powered devices using a "phased activation" of a load. This staged power-up, by successively increasing current consumption in increments rather than all at once, is intended to mitigate excessive transitory drops in the battery's supply voltage that can cause system resets or other problems.

3. Grounds for Unpatentability

Ground 1: Anticipation over Nagai - Claims 1, 2, 4, 5, 7, 9, 15, and 17 are anticipated by Nagai under 35 U.S.C. §102(a).

• Prior Art Relied Upon: Nagai (Japanese Patent Application Disclosure No. P2000-287371).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nagai discloses every limitation of the challenged claims. Nagai teaches a method to solve the same problem of voltage fluctuation at startup by powering a load circuit (element 20) that is divided into a plurality of sub-circuits (22a-22n). These sub-circuits are powered up sequentially at "mutually different timings" to make the startup voltage fluctuation "become small." This staged activation of multiple load circuits directly maps to the ’365 patent's "phased activation of a function." Nagai also explicitly teaches modeling the battery supply curve to estimate and wait for a predetermined time interval (e.g., 100 ms) for the voltage to recover before activating the next stage, anticipating the limitations of claims 4, 15, and 17. For the means-plus-function claims (7, 9, 17), Petitioner asserted that Nagai’s "voltage detection circuit 15," which controls the staged power-up, performs complex tasks (storing values, comparing, performing arithmetic) that a POSITA would understand to be a microcontroller or an equivalent structure to the ’365 patent's disclosed microcontroller 40.

Ground 2: Anticipation over Herrell - Claims 1, 2, 4, 5, 7, 9, 15, and 17 are anticipated by Herrell under 35 U.S.C. §102(b).

• Prior Art Relied Upon: Herrell (Patent 5,963,023).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Herrell as an alternative basis for anticipation, particularly if the claim term "function" is construed narrowly to cover only a single-load implementation, as argued by the patentee during prosecution. Herrell discloses mitigating voltage undershoot in a battery-powered microprocessor (a single load) by incrementally increasing its operating frequency in stages (e.g., from 0 MHz to 200 MHz, then to 300 MHz, etc.) rather than transitioning to full frequency at once. This "chirping the clock" constitutes a phased activation within a single load. Herrell further teaches modeling the power distribution system's transient response and waiting for a time interval (e.g., "about 60 ns") for each transient to "die[] away" before the next frequency increase, anticipating claims 4, 15, and 17. Petitioner argued that Herrell’s disclosed "feedback control circuitry" is the corresponding structure for the means-plus-function limitations, as a POSITA would understand it to be implemented with a microcontroller or equivalent.

Ground 3: Obviousness over Nagai in view of Gold - Claims 4, 15, and 17 are obvious over Nagai in view of Gold under 35 U.S.C. §103.

• Prior Art Relied Upon: Nagai (Japanese Patent Application Disclosure No. P2000-287371) and Gold (A PSPICE Macromodel for Lithium-Ion Batteries, 1997).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground was presented as a fallback in case Nagai’s disclosure was deemed insufficient to teach the "modeling a battery supply curve" limitations of claims 4, 15, and 17. Petitioner contended that Nagai teaches the core method of staged power-up with waiting intervals. Gold explicitly discloses using PSPICE, a well-known simulation tool, to create detailed battery models for simulating "transient response, and related characteristics." Gold’s detailed modeling techniques would have supplied any missing detail for the modeling and estimating limitations.
  • Motivation to Combine: A POSITA implementing Nagai's system would be motivated to accurately determine the voltage-settling time required between activating load stages. To improve upon Nagai’s simpler estimation, a POSITA would combine Nagai's method with the known, more sophisticated battery modeling techniques taught by Gold to better estimate transient response and optimize the waiting intervals.
  • Expectation of Success: Combining a known power-up scheme (Nagai) with a standard industry tool for battery analysis (Gold) to refine that scheme's timing parameters would have been a straightforward application of known principles with a high expectation of success.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 16 is obvious over Nagai or Herrell in view of POSITA knowledge. Further grounds argued claims 1, 2, 4, 5, 7, 9, 15, and 17 are obvious over the combination of Nagai and Herrell, and that claims 4, 15, and 17 are obvious over various combinations including Gold (e.g., Herrell and Gold; Nagai, Herrell, and Gold).

4. Key Claim Construction Positions

• "phased activation": Petitioner proposed this term should be construed as "a succession of incremental increases during power-up." This construction was argued to be broad enough to encompass both the successive power-up of multiple distinct loads (as taught by Nagai) and the incremental increase of a parameter for a single load (as taught by Herrell).
• "function": Petitioner proposed this term should be construed as "a current drawing load capable of powering-up in stages." This interpretation supports the invalidity arguments by defining "function" as the load itself, whether it is a single component or composed of multiple sub-circuits.
• Means-Plus-Function Limitations: For claims 7, 9, and 17, Petitioner identified the corresponding structure in the ’365 patent as "microcontroller 40" or an equivalent thereof, programmed to perform the claimed functions of effecting activation, increasing the function in sequence, and waiting for an estimated time interval.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1, 2, 4, 5, 7, 9, and 15-17 of Patent 6,590,365 as unpatentable.