PTAB

IPR2015-01198

Samsung Electronics Co Ltd v. NVIDIA Corp

Log In
Key Events
Petition
petition Intelligence

1. Case Identification

2. Patent Overview

  • Title: Method and apparatus for multithreaded processing of data in a programmable graphics processor
  • Brief Description: The ’913 patent describes a programmable graphics processor designed to overcome processing stalls common in traditional graphics pipelines where data is processed sequentially. The invention purports to solve this "stall" problem by processing graphics data elements (samples) in an order independent of their arrival. It discloses a multithreaded processing unit comprising three key components: an instruction scheduler that determines which instructions can be executed based on resource availability, a resource tracker (e.g., a scoreboard) that monitors the status of source data and processing units, and a dispatcher that outputs ready instructions to an execution unit for out-of-order execution.

3. Grounds for Unpatentability

Ground 1: Claims 5-10, 12-20, and 24-27 are obvious over Whittaker in view of Van Hook.

  • Prior Art Relied Upon: Whittaker (Patent 5,968,167) and Van Hook (Patent 7,847,803).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Whittaker and Van Hook teaches every limitation of the challenged claims, particularly the core features of independent claims 5, 17, and 20.
      • For independent claim 5 (apparatus): Petitioner asserted that Whittaker disclosed the core architecture. The claimed "multithreaded processing unit" was mapped to Whittaker’s "media control core" (MCC), a fine-grained multithreading unit. The "scheduler" and "resource tracking unit" were mapped to Whittaker’s MCC and its associated "resource checking logic," which checks for available data and processing resources on every clock cycle. The "dispatcher" was mapped to Whittaker's control unit and priority selector, which start execution of the highest-priority thread with available resources. Petitioner contended Van Hook supplied the specific context of applying this architecture to a "graphics processor" that interleaves programs for graphical elements like vertices and pixels.
      • For independent claim 17 (computing system): This claim adds a "host processor" and "system interface" to the graphics processor of claim 5. Petitioner mapped these elements primarily to Van Hook, which explicitly discloses a general-purpose CPU acting as a host that writes graphics data and commands to the interleaved graphics processor via an interface. Petitioner argued a POSITA would have been motivated to couple Whittaker’s multimedia coprocessor with a host CPU in the manner taught by Van Hook.
      • For independent claim 20 (method): The method steps were argued to mirror the functionality of the apparatus. The step of "determining that first source data... are not available" while "second source data... are available" was mapped to Whittaker's fundamental operation of checking all threads for resource availability. The step of "dispatching the second program instruction... prior to dispatching the first" was argued to be the direct result of Whittaker’s priority-based scheduling, where a stalled thread is passed over in favor of a ready thread.
      • For dependent claims: Petitioner asserted that additional limitations, such as processing "samples" like vertices and pixels (claim 6), using a "thread control buffer" (claim 7), and maintaining "thread state data" (claim 15), were also disclosed by the combination.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would be motivated to combine the references to solve the well-known and long-standing problem of pipeline stalls in graphics processing. A POSITA, facing the design challenge of improving graphics throughput, would look to known solutions for out-of-order execution. Petitioner argued that combining Whittaker’s established multithreaded processing architecture with the graphics-specific multithreading teachings of Van Hook was a straightforward application of a known technique to a similar problem to obtain predictable results. Both patents address performance optimization through multithreading and resource management, making the combination obvious to try.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because both patents address performance optimization through multithreading and resource management. Applying Whittaker's proven out-of-order execution core to the graphics processing domain described by Van Hook was presented as a predictable integration of compatible technologies that would successfully improve performance.

4. Key Claim Construction Positions

  • "samples": Petitioner proposed the broadest reasonable construction is "data, such as surfaces, primitives, vertices, pixels or fragments," based on definitions within the ’913 patent's specification. This broad definition was used to argue that the data processed by Whittaker (e.g., multimedia data for 3D graphics) and Van Hook (e.g., vertices, pixels) met this claim limitation.
  • "graphics processor": For claims 5-10 and 12-16, Petitioner argued this preamble term is not a limitation because the claim body recites a structurally complete "multithreaded processing unit" and the preamble only states an intended use. For claim 17, where the term appears in the body, Petitioner proposed the construction "hardware capable of processing graphics data."

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 5-10, 12-20, and 24-27 of the ’913 patent as unpatentable under 35 U.S.C. §103.