PTAB

IPR2015-01524

Samsung Electronics Co Ltd v. Elbrus Intl Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Data Transfer Scheme Including a Latching Sense Amplifier
  • Brief Description: The ’130 patent discloses a data transfer arrangement for electronic circuits. The system uses two bus drivers, a precharge source, a differential bus, and a two-stage latching sense amplifier to increase data transfer speed and reduce power consumption.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sukegawa and Lu - Claims 1-2, 5-6, and 9 are obvious over Sukegawa in view of Lu.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241) and Lu ("Half-VDD Bit-Line Sensing Scheme in CMOS DRAM's," IEEE Journal of Solid-State Circuits, Aug. 1984).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sukegawa, which describes a signal transmission circuit to increase speed and reduce power consumption, disclosed nearly all limitations of independent claim 1. Specifically, Sukegawa taught a data transfer arrangement with two bus drivers, a differential bus (LINE/LINE_), a voltage precharge source (BLR providing VDD/2), and a latching sense amplifier. Petitioner mapped Sukegawa’s intermediate amplifier (circuit 1) and receiver circuit (circuit 4) to the claimed "first stage" and "output stage" of the latching sense amplifier, respectively. Petitioner contended the only missing element was precharging the differential data bus (the internal bus of the output stage) to an intermediate voltage. Sukegawa precharged this bus to Vdd. Lu was introduced to supply this element, as it explicitly taught the benefits of precharging bit lines to half-VDD to achieve faster, more balanced pull-up and pull-down, thereby reducing voltage swing and increasing speed.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Lu’s well-known half-VDD precharging technique with Sukegawa’s circuit to gain the predictable benefit of increased operational speed. Both references addressed the same technical problem of improving signal transmission efficiency in electronic circuits. Applying Lu's technique to Sukegawa’s differential data bus was presented as a simple application of a known method to a similar device to yield predictable results.
    • Expectation of Success: A POSITA would have a high expectation of success, as precharging to an intermediate voltage was a standard, well-understood technique for improving circuit performance.

Ground 2: Obviousness over Sukegawa, Lu, and Watanabe - Claim 3 is obvious over Sukegawa in view of Lu and Watanabe.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241), Lu (IEEE Journal, Aug. 1984), and Watanabe (Patent 6,108,254).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination of Sukegawa and Lu to address the specific transistor-level limitations of the "first stage" recited in dependent claim 3. Petitioner argued that while Sukegawa disclosed a first stage, Watanabe taught a more efficient first-stage data latch circuit that explicitly met the detailed limitations of claim 3. These limitations included a plurality of input pass transistors and specific couplings for the NMOS and PMOS transistors within the cross-coupled latch amplifier. Petitioner contended that a POSITA would find it obvious to replace the first stage of the Sukegawa/Lu combination with the more advantageous first stage disclosed in Watanabe.
    • Motivation to Combine: A POSITA would be motivated to modify the Sukegawa/Lu circuit with Watanabe's first stage for several known benefits. Watanabe's design used fewer transistors and control signals, which would predictably speed up circuit operation and allow for a smaller, more compact circuit layout. These were strong, well-understood motivations in the field of integrated circuit design.
    • Expectation of Success: The proposed modification was argued to be a straightforward substitution of one known functional block (a latching amplifier stage) with another known, more efficient version to achieve predictable improvements in speed and density.

Ground 3: Obviousness over Sukegawa, Lu, and Hardee - Claim 7 is obvious over Sukegawa in view of Lu and Hardee.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241), Lu (IEEE Journal, Aug. 1984), and Hardee (Patent 6,249,469).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claim 7, which required the active pull-up and pull-down bus drivers to be constructed entirely of NMOS transistors. The primary reference, Sukegawa, disclosed a CMOS design using both PMOS (pull-up) and NMOS (pull-down) transistors. Petitioner argued that Hardee explicitly taught the use of all-NMOS transistors for both pull-up and pull-down bus drivers. A POSITA would have found it obvious to modify the bus drivers in the Sukegawa/Lu combination to use the all-NMOS configuration taught by Hardee.
    • Motivation to Combine: Petitioner asserted clear motivations for this modification based on Hardee. Using only NMOS transistors was a known design choice that provided two key advantages: 1) it reduced the circuit layout area by eliminating the need for separate n-wells required for PMOS transistors, and 2) it made the driver circuit immune to "latch-up," a common and destructive failure mode in CMOS circuits.
    • Expectation of Success: Modifying a CMOS driver to be an all-NMOS driver was presented as a simple design choice from a small, finite number of known driver configurations. A POSITA would have readily understood the modification and expected the predictable benefits of smaller size and improved reliability.

4. Key Claim Construction Positions

  • "latching sense amplifier" (claims 1, 3): Petitioner proposed this term be construed to mean "a circuit, including a latch, that detects and amplifies signals." This construction was argued to be consistent with the patent's specification and the understanding of a POSITA, supported by dictionary definitions. It was foundational to mapping Sukegawa’s separate intermediate amplifier and receiver circuits onto the claimed two-stage structure.
  • "stage" (claims 1, 3, 9): Petitioner proposed this term be construed to mean "portion of a circuit." This construction allowed Petitioner to argue that distinct parts of the prior art circuits, like Sukegawa's amplifier and receiver, could be considered separate "stages" of a single, larger latching sense amplifier, even if not explicitly labeled as such in the prior art.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-7, and 9 of the ’130 patent as unpatentable.