PTAB

IPR2015-01675

Smart Modular Technologies Inc v. James Goodman

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Volatile Memory System with Low-Power Data Retention
  • Brief Description: The ’315 patent discloses a memory system for use in a computer that can retain data in volatile memory devices during low-power situations. The system uses a control device to electrically isolate the memory devices from address and control lines and place them into a self-refresh mode, thereby reducing power consumption.

3. Grounds for Unpatentability

Ground 1: Obviousness over Schaefer and Qureshi - Claims 1 and 5 are obvious over Schaefer in view of Qureshi.

  • Prior Art Relied Upon: Schaefer (Patent 5,600,605) and Qureshi (Patent 5,793,776).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Schaefer taught all the core components of a JEDEC-compliant memory system, including a plurality of volatile solid-state memory devices (specifically, an SDRAM with multiple memory banks) capable of entering a low-power "SELF-REFRESH command" mode. However, Schaefer allegedly lacked a specific memory controller for initiating this mode. Petitioner asserted that Qureshi supplied this missing element, teaching a memory controller (the claimed "control device") explicitly designed to place an SDRAM into a self-refresh mode. In this mode, Qureshi’s controller causes the SDRAM to ignore all external inputs except the clock enable signal, thereby achieving the claimed "electrical isolation" and reducing power consumption. Dependent claim 5, requiring the memory to be DRAM, was argued to be met because SDRAM is a type of DRAM taught by both references.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine the references because they describe complementary, interoperable components of a standard memory system. Qureshi taught a controller for managing SDRAM, and Schaefer taught just such an SDRAM. Combining them would achieve the predictable and desirable goal of creating a memory system capable of low-power data retention, a well-known objective in the field.
    • Expectation of Success: A POSITA would have a high expectation of success, as the combination involved integrating standardized, JEDEC-compliant components (a controller and memory) that were designed to work together according to established industry protocols.

Ground 2: Obviousness over Schaefer, Qureshi, and Mazur - Claims 10 and 16 are obvious over Schaefer in view of Qureshi and Mazur.

  • Prior Art Relied Upon: Schaefer (Patent 5,600,605), Qureshi (Patent 5,793,776), and Mazur (Patent 5,204,840).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground incorporated the Schaefer/Qureshi combination from Ground 1 to teach the base memory system of claim 10. Petitioner argued that Mazur taught the remaining limitations related to a secondary power source. Specifically, Mazur disclosed a complete backup power system for DRAM, including a power loss detection circuit to monitor the primary voltage, a "second electrical power source" (a rechargeable battery), and a switch-over circuit. This circuit would automatically disconnect the primary power and connect the battery when the primary voltage dropped below a predetermined level (e.g., 4.8V), ensuring data preservation. Mazur also taught that its circuitry isolated the DRAM from the main computer during backup operation, preventing data corruption from errant signals.
    • Motivation to Combine: A POSITA, having created the low-power data retention system of Schaefer and Qureshi, would be motivated to add Mazur's teachings to make the system more robust. Protecting volatile memory against primary power failure using a battery backup was a common and well-understood engineering goal. Mazur provided a known solution to this known problem, which would be a logical improvement to the base combination.
    • Expectation of Success: Success would be highly predictable. Adding a backup battery circuit to a low-power electronic device was a conventional and well-established practice in the art, and Mazur provided a detailed blueprint for its implementation.

4. Key Claim Construction Positions

  • Petitioner argued that, for the purposes of the inter partes review (IPR), claim terms should be given their broadest reasonable interpretation consistent with the specification and the Patent Owner's own infringement contentions from related district court litigation. This approach centered on construing the claims to encompass systems compliant with JEDEC industry standards for memory devices.
  • "A Memory System For Use In A Computer System" (Claims 1 & 10): Petitioner proposed this preamble term be construed as "a JEDEC-compliant system with memory devices connected to a memory controller."
  • "A Control Device For Selectively Electrically Isolating..." (Claims 1 & 10): Petitioner proposed this term be construed as "a memory controller for providing a JEDEC-compliant signal to trigger a 'don't care' or inhibit action for the corresponding memory devices," aligning the concept of "isolating" with the standard JEDEC self-refresh state where inputs are ignored.
  • "A low power mode" (Claims 1 & 10): Petitioner proposed this term be construed as "a JEDEC-compliant low power mode or 'power down mode'," directly tying the claim language to standard features described in JEDEC specifications.

5. Relief Requested

  • Petitioner requests institution of an IPR and cancellation of claims 1, 5, 10, and 16 of Patent 6,243,315 as unpatentable.