PTAB

IPR2015-01812

Intel Corp v. Memory Integrity LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Techniques for Processing Memory Transactions in a Computer System
  • Brief Description: The ’254 patent describes techniques for addressing a "transaction processing bottleneck" in multiprocessor computer systems. The invention involves using multiple protocol engines within an interconnection controller, dividing the processing workload by assigning different engines to handle memory transactions directed to either local memory or remote memory based on the transaction's target address.

3. Grounds for Unpatentability

Ground 1: Obviousness over Nanda and Pragaspathy - Claims 1 and 8 are obvious over Nanda in view of Pragaspathy.

  • Prior Art Relied Upon: Nanda ("High-Throughput Coherence Control and Hardware Messaging in Everest," IBM Journal, Mar. 2001) and Pragaspathy ("Address Partitioning in DSM Clusters with Parallel Coherence Controllers," IEEE Proc., Oct. 2000).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Nanda, which was not considered during prosecution, discloses nearly every limitation of independent claim 1. Nanda describes the "Everest" architecture, which addresses the same memory transaction bottleneck identified in the ’254 patent. It does so by using multiple protocol engines, explicitly distinguishing between Remote Protocol Engines (RPEs) for handling remote memory requests and Local Protocol Engines (LPEs) for local memory requests. Nanda teaches that each of these engines is assigned a distinct, non-overlapping region of physical memory. For claim 8, which requires the memory subsets to be mutually exclusive, Petitioner contended Nanda's teaching of "non-overlapping" memory regions meets this limitation.
    • Motivation to Combine (for §103 grounds): Petitioner asserted that while Nanda necessarily implies selection circuitry to route transactions, Pragaspathy was cited to explicitly disclose this element. Pragaspathy teaches using an "address demultiplexer" to select a protocol engine from among multiple engines based on address bits in a memory request. A person of ordinary skill in the art (POSITA) would combine Pragaspathy’s explicit selection circuitry with Nanda’s architecture as an obvious design choice, as both references are in the same field and address the same problem of partitioning memory transactions among multiple protocol engines.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because implementing a known selection circuit (Pragaspathy's demultiplexer) into a multiprocessor system with distinct protocol engines (Nanda) was a well-understood technique to improve system performance.

Ground 2: Obviousness over Nanda, Pragaspathy, and Culler - Claims 2-5 are obvious over Nanda in view of Pragaspathy and Culler.

  • Prior Art Relied Upon: Nanda, Pragaspathy, and Culler ("Parallel Computer Architecture," 1999).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds on Ground 1 to address dependent claims 2-4, which require the processing nodes and interconnection controller to be interconnected via a "point-to-point architecture" (including ring and mesh topologies, claims 3 and 4). Petitioner argued that Nanda discloses a bus-based architecture, which was known to have scaling limitations. Culler, a textbook on computer architecture, explicitly teaches replacing bus-based systems with more scalable point-to-point networks to solve these known limitations. Culler describes various point-to-point topologies, including the claimed ring and mesh configurations. For claim 5, Petitioner argued Nanda discloses that a transaction's target address, contained within a packet, is used as the destination information.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Culler's teachings with the Nanda/Pragaspathy system to improve its scalability. Replacing a bus with a point-to-point network was a well-known design choice for multiprocessor systems to overcome performance bottlenecks. Culler presents this modification not as an inventive leap but as a known, superior alternative for scalable systems.
    • Expectation of Success (for §103 grounds): The combination would have been straightforward, as Culler provides detailed instruction on implementing various point-to-point architectures and their associated coherence protocols in systems like Nanda's.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 6 and 7. These grounds relied on the core combination of Nanda, Pragaspathy, and Culler, adding Bauman (Patent 6,415,364) to teach locating the selection circuitry within a processing node (claim 6) and Piranha (a 2000 ACM publication) to teach a dedicated protocol engine for processing interrupts (claim 7).

4. Key Claim Construction Positions

  • Petitioner argued for construing the key limitation present in independent claim 1: "a first protocol engine configured to be assigned a first subset of the global memory space, said first subset... corresponding to one of local and remote memory".
  • Proposed Construction: "a first protocol engine configured to be assigned addresses for one of either local or remote memory in a global memory space".
  • Rationale: Petitioner contended this construction was required for three reasons. First, the plain language of "one of" means either/or, but not both, especially when the applicants used "at least one of" elsewhere in the claims to mean something different. Second, the specification consistently describes distinct "remote memory protocol engines" and "local memory protocol engines," with no embodiment disclosing an engine that handles both. Third, during prosecution, the Patent Owner overcame a rejection by amending the claims to add this "one of" language, arguing that the "unique nature" of the invention was that engines were assigned to either local or remote memory, thereby disclaiming a broader scope.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of Patent 8,898,254 as unpatentable under 35 U.S.C. §103.