PTAB

IPR2015-01861

Qualcomm Inc v. NVIDIA Corp

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1. Case Identification

2. Patent Overview

  • Title: Programmable Graphics Processor for Multithreaded Execution of Programs
  • Brief Description: The ’685 patent describes a graphics processor architecture designed to improve hardware utilization. It discloses a single Programmable Computation Unit (PCU) capable of processing multiple types of graphics data, such as vertex and pixel data (a "unified shader"), within a multithreaded environment to dynamically balance workloads.

3. Grounds for Unpatentability

Ground 1: Obviousness over Amanatides, Van Hook, and Fiske - Claims 1-19, 21-23, 25-30, 34-36, and 38-43 are obvious over Amanatides in view of Van Hook and Fiske.

  • Prior Art Relied Upon: Amanatides (a 1993 publication titled "A simple, flexible, parallel graphics architecture"), Van Hook (Patent 7,847,803), and Fiske (a 1995 dissertation titled "Thread scheduling mechanisms for multiple-context parallel processors").
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that the combination of these references, none of which were before the Examiner during prosecution, teaches every element of the challenged claims. Amanatides, published a decade before the ’685 patent, disclosed the core concept of a unified shader architecture where parallel processors can perform both vertex ("Geometry") and pixel ("Rendering") processing. It explicitly taught using high and low priorities for these task types to achieve "auto load balancing." However, Amanatides used a multiprocessor architecture, not a multithreaded one.

    • Van Hook disclosed a programmable, multithreaded 3D graphics processor that improves efficiency by rapidly switching between threads, a known benefit particularly suited for the high volume of parallel tasks in graphics. Van Hook’s architecture provides the claimed "multithreaded processing unit" with a "thread control unit" (its interleaver) and a "thread storage resource" (its program counters and registers for each thread).

    • Fiske provided the fundamental teachings on multithreaded scheduling, describing "thread prioritization" as a simple and known method for making scheduling decisions, such as which threads to load and which to execute.

    • Petitioner asserted that a POSITA would have combined these teachings by implementing Amanatides' unified shader concept within Van Hook's more efficient multithreaded architecture. In this combination, the task-based priorities of Amanatides (e.g., high priority for pixel work, low for vertex work) would be implemented as the thread priorities described by Fiske to manage thread allocation and execution. This combination directly results in a system that dynamically balances sample types among threads based on an allocation priority, as claimed.

    • Motivation to Combine: Petitioner provided several rationales for why a person of ordinary skill in the art (POSITA) would combine the references. First, it was well-known that transitioning from a multiprocessor architecture (like Amanatides) to a multithreaded architecture (like Van Hook) predictably increased processor utilization and throughput. Second, the nature of 3D graphics processing, with its large number of independent tasks, was known to be an ideal application for the benefits of multithreading. Third, the move from multiprocessor to single-chip multithreaded designs was a general industry trend in the late 1990s and early 2000s, driven by advances in semiconductor fabrication that made such designs more practical.

    • Expectation of Success: Petitioner argued the combination was a straightforward adaptation that would yield predictable results. A POSITA would understand that the parallel physical processors in Amanatides naturally correspond to the parallel threads ("logical processors") in Van Hook's architecture. Implementing Fiske's "simple" thread prioritization scheme was a necessary and obvious design choice to manage the scheduling decisions inherent in any multithreaded system. The combination required no undue experimentation and would have been a predictable evolution of known graphics processing concepts.

4. Key Claim Construction Positions

  • "graphics processor": Petitioner argued that this term, appearing in the preamble of claims 1-5, 7-19, 21, and 22, is not a limitation because it provides no antecedent basis and does not give life or meaning to the claims. Should the Board find the term limiting, Petitioner contended its broadest reasonable interpretation is "hardware capable of processing graphics data," without being restricted to a dedicated graphics processing component.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-19, 21-23, 25-30, 34-36, and 38-43 of the ’685 patent as unpatentable.