Qualcomm Inc v. NVIDIA Corp

1. Case Identification

• Case #: IPR2015-01863
• Patent #: Patent 7,038,685
• Filed: September 4, 2015
• Petitioner(s): Qualcomm Inc
• Patent Owner(s): NVIDIA Corp
• Challenged Claims: 1-19, 21-23, 25-30, 34-36, 38-43

2. Patent Overview

• Title: Programmable Graphics Processor for Multithreaded Execution of Programs
• Brief Description: The ’685 patent discloses a graphics processor with a unified shader architecture, where a single programmable computation unit (PCU) can process multiple data sample types (e.g., vertex and pixel data). The system uses a multithreaded architecture to dynamically assign and execute tasks based on priorities to improve hardware utilization and prevent processing units from becoming underutilized.

3. Grounds for Unpatentability

Ground 1: Obviousness over Selzer and Fiske - Claims 1-13, 15-18, 21-23, 25-30, 34-36, and 38-43 are obvious over Selzer in view of Fiske.

• Prior Art Relied Upon: Selzer (a 1993 conference proceeding on high-performance graphics systems) and Fiske (a 1995 dissertation on thread scheduling for parallel processors).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Selzer taught a unified shader system using parallel processors ("rendering modules") capable of processing both vertex ("geometry") and pixel ("rendering") data. Selzer also disclosed a priority scheme where pixel processing is prioritized over vertex processing to achieve dynamic load balancing and maximize processor utilization. Petitioner asserted that Fiske taught the fundamental components and well-known benefits of a general-purpose multithreaded architecture, which improves processor utilization over multiprocessor systems like Selzer’s by better tolerating memory latency. Fiske explicitly disclosed using "thread prioritization" to manage thread scheduling decisions (e.g., which thread to execute next), which Petitioner contended directly corresponds to the priority-based load balancing in Selzer.
  • Motivation to Combine: A POSITA would combine Selzer's unified shader concept with Fiske's more efficient multithreaded architecture to achieve the known and predictable benefits of increased processor utilization and reduced idle time. Petitioner contended that transitioning from a multiprocessor architecture to a multithreaded one was a known design choice at the time, and the highly parallelizable nature of graphics processing made it an especially suitable application for such an improvement. The combination represented the substitution of one known parallel processing architecture for another to gain a predictable advantage.
  • Expectation of Success: The combination was presented as a straightforward adaptation. A POSITA would have predictably mapped Selzer's parallel physical processors to Fiske's parallel logical threads ("contexts") and applied Selzer's data-type priority scheme (pixel over vertex) using Fiske's disclosed "thread prioritization" mechanism for both thread allocation and execution decisions.

Ground 2: Obviousness over Selzer, Fiske, and Van Hook - Claims 14 and 19 are obvious over Selzer in view of Fiske and Van Hook.

• Prior Art Relied Upon: Selzer (a 1993 conference proceeding), Fiske (a 1995 dissertation), and Van Hook (Patent 7,847,803).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the primary combination of Selzer and Fiske to address additional limitations in claims 14 and 19 related to input buffers and pixel data sorting. Petitioner argued that Van Hook taught a programmable multithreaded graphics processor that used separate, dedicated "hardwired graphics processing" circuitry for tasks like polygon rasterization. This approach was described as a well-known configuration for improving speed and efficiency. The output of Van Hook’s hardwired rasterizer could then feed the input buffer of the main programmable processor. Van Hook also disclosed pre-sorting pixel data based on output position to ensure correct rendering order.
  • Motivation to Combine: A POSITA would be motivated to incorporate Van Hook's use of a separate hardwired rasterizer into the Selzer/Fiske system as a simple design choice to gain the known advantages of speed and efficiency for that specific task. This predictable modification would result in a system having the pixel input buffer coupled to the thread control unit, as required by claim 14. Furthermore, incorporating Van Hook's pixel sorting mechanism was argued to be an obvious addition to the combined system to ensure proper data ordering, a common requirement in graphics pipelines, thus teaching the limitations of claim 19.
  • Expectation of Success: Petitioner asserted that incorporating a well-known graphics pipeline component like a dedicated rasterizer and a data sorting function from Van Hook into the base multithreaded unified shader architecture would have been a predictable design modification for a POSITA.

4. Key Claim Construction Positions

• "graphics processor": Petitioner argued this preamble term is not limiting. If the Board were to find it limiting, its broadest reasonable interpretation should be "hardware capable of processing graphics data," without being restricted to a dedicated graphics component.
• "the instructions associated with the sample... are different from sample to sample": Petitioner asserted the plain language of this phrase, which appears in claim 26, simply means there is no specific temporal relationship between the referenced samples.
• "third number of processing threads": For claims 34 and 35, Petitioner argued this phrase does not require the "third number" of threads to exist simultaneously with a "first number" of threads, asserting this interpretation is consistent with the patent's figures and description.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-19, 21-23, 25-30, 34-36, and 38-43 of the ’685 patent as unpatentable under 35 U.S.C. § 103.